From patchwork Wed Dec 7 01:43:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Asahi Lina X-Patchwork-Id: 631725 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58A76C352A1 for ; Wed, 7 Dec 2022 01:43:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229536AbiLGBnP (ORCPT ); Tue, 6 Dec 2022 20:43:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229487AbiLGBnO (ORCPT ); Tue, 6 Dec 2022 20:43:14 -0500 Received: from mail.marcansoft.com (marcansoft.com [212.63.210.85]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F5CB2EF7F; Tue, 6 Dec 2022 17:43:13 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: linasend@asahilina.net) by mail.marcansoft.com (Postfix) with ESMTPSA id 26E8341F98; Wed, 7 Dec 2022 01:43:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=asahilina.net; s=default; t=1670377391; bh=oQYgSBif56vxQdHFPOTELw3/FtXZ0hY2uV7LPeyLQYs=; h=From:To:Cc:Subject:Date; b=HCE3UUQovp4m++sguRpMIpV5m8Chben63rZo237wf3Dc1927wq3OLdQWw1t266w9S NZ1VVhw5roYnij+8QGPc/Zg4cGDTbG6LEkKL7EnfrGzbPXpbmhatlVLxGyZMOGbPSL alW5AJBl+84fd9M5I/rwPnew4tfZ0q7zFiZjZLgx/gYIl5AX8WVQTvj1b2CAoIQNyQ lUSkZnDaMK1ttxuYjm+/XAofHFL/oUmyXDuv7txjWlcyJU8I+UxWpmEFkY2DPe3AW5 TfIq9xaA7U3uU53NIz6BWwFN34rPGFK2F3a1hY35rWDal0jzXgzv59F4txcujdbjld 7h5egZNVWrrtw== From: Asahi Lina To: Hector Martin , Sven Peter , Alyssa Rosenzweig , Janne Grunau Cc: Marc Zyngier , asahi@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Asahi Lina Subject: [PATCH] arm64: dts: apple: t6002: Fix GPU power domains Date: Wed, 7 Dec 2022 10:43:04 +0900 Message-Id: <20221207014305.21018-1-lina@asahilina.net> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On t6002 (M1 Ultra), each die contains a self-contained GPU block. However, only the coprocessor and global management circuitry of the first die are used. This is what is represented by the "gpu" PS (the one in die1 is disabled). Nonetheless, this shared component drives the processing blocks in both dies, and therefore depends on the AFR fabric being powered up on both dies. Add an explicit dependency from the GPU block on die0 to AFR on die1, next to the existing die0 AFR dependency. Fixes: fa86294eb355 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs") Signed-off-by: Asahi Lina Reviewed-by: Janne Grunau --- arch/arm64/boot/dts/apple/t6002.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi index 1376103b49c6..8fa2d8dd72ff 100644 --- a/arch/arm64/boot/dts/apple/t6002.dtsi +++ b/arch/arm64/boot/dts/apple/t6002.dtsi @@ -296,3 +296,8 @@ &cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23 }; }; }; + +&ps_gfx { + // On t6002, the die0 GPU power domain needs both AFR power domains + power-domains = <&ps_afr>, <&ps_afr_die1>; +};