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[88.156.142.67]) by smtp.gmail.com with ESMTPSA id p1-20020ac24ec1000000b004991437990esm657494lfr.11.2022.12.01.05.30.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 05:30:38 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] dt-bindings: serial: qcom,msm-uart: Convert to DT schema Date: Thu, 1 Dec 2022 14:30:36 +0100 Message-Id: <20221201133036.45288-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Qualcomm MSM SoC UART (non-DMA) bindings to DT schema. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/serial/qcom,msm-uart.txt | 25 --------- .../bindings/serial/qcom,msm-uart.yaml | 56 +++++++++++++++++++ 2 files changed, 56 insertions(+), 25 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/qcom,msm-uart.txt create mode 100644 Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt deleted file mode 100644 index ce8c90161959..000000000000 --- a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt +++ /dev/null @@ -1,25 +0,0 @@ -* MSM Serial UART - -The MSM serial UART hardware is designed for low-speed use cases where a -dma-engine isn't needed. From a software perspective it's mostly compatible -with the MSM serial UARTDM except that it only supports reading and writing one -character at a time. - -Required properties: -- compatible: Should contain "qcom,msm-uart" -- reg: Should contain UART register location and length. -- interrupts: Should contain UART interrupt. -- clocks: Should contain the core clock. -- clock-names: Should be "core". - -Example: - -A uart device at 0xa9c00000 with interrupt 11. - -serial@a9c00000 { - compatible = "qcom,msm-uart"; - reg = <0xa9c00000 0x1000>; - interrupts = <11>; - clocks = <&uart_cxc>; - clock-names = "core"; -}; diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml new file mode 100644 index 000000000000..a052aaef21f4 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qcom,msm-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM SoC Serial UART + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The MSM serial UART hardware is designed for low-speed use cases where a + dma-engine isn't needed. From a software perspective it's mostly compatible + with the MSM serial UARTDM except that it only supports reading and writing + one character at a time. + +properties: + compatible: + const: qcom,msm-uart + + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clock-names + - clocks + - interrupts + - reg + +unevaluatedProperties: false + +allOf: + - $ref: /schemas/serial/serial.yaml# + +examples: + - | + serial@a9c00000 { + compatible = "qcom,msm-uart"; + reg = <0xa9c00000 0x1000>; + interrupts = <11>; + clocks = <&uart_cxc>; + clock-names = "core"; + };