From patchwork Wed Nov 23 21:03:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 628093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0A2AC3A59F for ; Wed, 23 Nov 2022 21:04:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237370AbiKWVE1 (ORCPT ); Wed, 23 Nov 2022 16:04:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237443AbiKWVEQ (ORCPT ); Wed, 23 Nov 2022 16:04:16 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69D4797A99 for ; Wed, 23 Nov 2022 13:04:10 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id g7so29972824lfv.5 for ; Wed, 23 Nov 2022 13:04:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JzVHcmxorROJCIoZd11bHlIHsRKO6twZzQN8g754tbQ=; b=nFaNPBxwoQUeOP54oU2tx6S9FR7YelHx27WEFXWu2cHhEid2Uc+Dxs1Im0f0A6qLhl sKMtqk5GecHvGjBexFvK7oDz0oJlu9pORO9xa2unYAwyIWmz4jx867vEtVRRrHXIKqp4 UFwdlz7HyN1R8H2RXlgA/SyW51ZAEtWcwqY6sewz9ldQiCIEFhfYAJZhhneaWCuffTAZ v4p5zJyGML4Khdam1NG0nQ04lI2x2jyb5Ctj6MiGtlJ2vDiNPhHWQQMZy/c++No860es aVMUM+QSyII+z7hIvIToiHE19Xz+4wAhxYdtBCMlu/2pEeqAjljFICejlxajxaMU6CRI mZRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JzVHcmxorROJCIoZd11bHlIHsRKO6twZzQN8g754tbQ=; b=nuSfYfX6S73s0FacKKBoUojKZkxb6o0ipxXztF5Y9etY7VhyVnxFqylmiC+naSEosa 6tTQtNiZN4HkHt7r6+BuZ3PFC7uCVst8600qPfhFiRWwKaDexTTewm/joQnlpFX6zw4z DUr1W64/H/S9Wu17IBelYU6xnLGv+eFZukUMFZYRjl7BBI8Z4M5P3d+LQkQMLvlnE1Ew R7zK4GRKI9QyYp6kyI0qWynER5PO5hxafscXYVOMveq1SUIM1Pw4F2iNZht+wO/Ahg+o gbrlpJavQY6LQbS8q373RizdqCKcEAHV1+9bSRMjQeAUQ+jXYPGsYExCMPpIAT1akpdz hOlg== X-Gm-Message-State: ANoB5pnSw/oG9ykX2TxAZszhCnP8IDvO3A7m7+iHYXiItMrdRVYhQ4nj 1Auc0yxmrDuUSZWlXdQY+3Iung== X-Google-Smtp-Source: AA0mqf5fNdtYcM2Pbvb4S8ZwzG7JXBqqwswezEyq8ghCbfoDfxeZv/69Kd5jc2D14MVJ5Qc0yrfZIw== X-Received: by 2002:a19:6b0b:0:b0:4a2:44dc:b70c with SMTP id d11-20020a196b0b000000b004a244dcb70cmr9183696lfa.360.1669237448428; Wed, 23 Nov 2022 13:04:08 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c3-20020ac25f63000000b004b177293a8dsm3009913lfc.210.2022.11.23.13.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 13:04:08 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio Subject: [PATCH v5 05/10] drm/msm/dsi/phy: rework register setting for 7nm PHY Date: Wed, 23 Nov 2022 23:03:58 +0200 Message-Id: <20221123210403.3593366-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> References: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation to adding the sm8350 and sm8450 PHYs support, rearrange register values calculations in dsi_7nm_phy_enable(). This change bears no functional changes itself, it is merely a preparation for the next patch. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 26 +++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 9e7fa7d88ead..0b780f9d3d0a 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -858,23 +858,34 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, /* Alter PHY configurations if data rate less than 1.5GHZ*/ less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); + if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; + vreg_ctrl_1 = 0x55; + glbl_pemph_ctrl_0 = 0x11; + lane_ctrl0 = 0x17; + } else { + vreg_ctrl_1 = 0x5c; + glbl_pemph_ctrl_0 = 0x00; + lane_ctrl0 = 0x1f; + } + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; if (phy->cphy_mode) { glbl_rescode_top_ctrl = 0x00; glbl_rescode_bot_ctrl = 0x3c; } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; } glbl_str_swi_cal_sel_ctrl = 0x00; glbl_hstx_str_ctrl_0 = 0x88; } else { - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; if (phy->cphy_mode) { glbl_str_swi_cal_sel_ctrl = 0x03; glbl_hstx_str_ctrl_0 = 0x66; } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; } @@ -882,17 +893,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, glbl_rescode_bot_ctrl = 0x3c; } - if (phy->cphy_mode) { - vreg_ctrl_0 = 0x51; - vreg_ctrl_1 = 0x55; - glbl_pemph_ctrl_0 = 0x11; - lane_ctrl0 = 0x17; - } else { - vreg_ctrl_1 = 0x5c; - glbl_pemph_ctrl_0 = 0x00; - lane_ctrl0 = 0x1f; - } - /* de-assert digital and pll power down */ data = BIT(6) | BIT(5); dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data);