From patchwork Tue Nov 22 16:32:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Gondois X-Patchwork-Id: 627631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E1D1C4332F for ; Tue, 22 Nov 2022 16:32:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232370AbiKVQcj (ORCPT ); Tue, 22 Nov 2022 11:32:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233779AbiKVQci (ORCPT ); Tue, 22 Nov 2022 11:32:38 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 93A31BCA6; Tue, 22 Nov 2022 08:32:34 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D1AAD23A; Tue, 22 Nov 2022 08:32:40 -0800 (PST) Received: from pierre123.arm.com (pierre123.nice.arm.com [10.34.100.128]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3730B3F73D; Tue, 22 Nov 2022 08:32:32 -0800 (PST) From: Pierre Gondois To: linux-kernel@vger.kernel.org Cc: Pierre Gondois , Rob Herring , Krzysztof Kozlowski , Florian Fainelli , Broadcom internal kernel review list , Ray Jui , Scott Branden , William Zhang , Anand Gore , Kursad Oney , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/2] arm: dts: Update cache properties for broadcom Date: Tue, 22 Nov 2022 17:32:06 +0100 Message-Id: <20221122163208.3810985-2-pierre.gondois@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221122163208.3810985-1-pierre.gondois@arm.com> References: <20221122163208.3810985-1-pierre.gondois@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois --- arch/arm/boot/dts/bcm2711.dtsi | 1 + arch/arm/boot/dts/bcm2836.dtsi | 1 + arch/arm/boot/dts/bcm2837.dtsi | 1 + arch/arm/boot/dts/bcm47622.dtsi | 1 + arch/arm/boot/dts/bcm63148.dtsi | 1 + arch/arm/boot/dts/bcm63178.dtsi | 1 + arch/arm/boot/dts/bcm6756.dtsi | 1 + arch/arm/boot/dts/bcm6846.dtsi | 1 + arch/arm/boot/dts/bcm6855.dtsi | 1 + arch/arm/boot/dts/bcm6878.dtsi | 1 + 10 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 941c4d16791b..c6104149f959 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -536,6 +536,7 @@ cpu3: cpu@3 { */ l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index 534dacfc4dd5..547ecc210f18 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -113,6 +113,7 @@ v7_cpu3: cpu@3 { */ l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index 5dbdebc46259..b352ac784af6 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -115,6 +115,7 @@ cpu3: cpu@3 { */ l2: l2-cache0 { compatible = "cache"; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi index 2df04528af82..f4b2db9bc4ab 100644 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -51,6 +51,7 @@ CA7_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi index df5307b6b3af..7cd55d64de71 100644 --- a/arch/arm/boot/dts/bcm63148.dtsi +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -35,6 +35,7 @@ B15_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi index cbd094dde6d0..043e699cbc27 100644 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -43,6 +43,7 @@ CA7_2: cpu@2 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi index ce1b59faf800..5c72219bc194 100644 --- a/arch/arm/boot/dts/bcm6756.dtsi +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -51,6 +51,7 @@ CA7_3: cpu@3 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi index 8aa47a2583b2..81513a793815 100644 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -35,6 +35,7 @@ CA7_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi index 620f51aee1a2..5fa5feac0e29 100644 --- a/arch/arm/boot/dts/bcm6855.dtsi +++ b/arch/arm/boot/dts/bcm6855.dtsi @@ -43,6 +43,7 @@ CA7_2: cpu@2 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi index 1e8b5fa96c25..4ec836ac4baf 100644 --- a/arch/arm/boot/dts/bcm6878.dtsi +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -35,6 +35,7 @@ CA7_1: cpu@1 { L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; };