From patchwork Sun Oct 30 15:55:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 620653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28838FA374E for ; Sun, 30 Oct 2022 15:55:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229678AbiJ3Pzg (ORCPT ); Sun, 30 Oct 2022 11:55:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229750AbiJ3Pze (ORCPT ); Sun, 30 Oct 2022 11:55:34 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB6612CC for ; Sun, 30 Oct 2022 08:55:31 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id b2so15818175lfp.6 for ; Sun, 30 Oct 2022 08:55:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VP/AAyYjw0Rr7hmFWioIleiT2CT56Mt2aJdhU6I1hPs=; b=UKv/rrXR7trksbK8a9cgbxWjk6rcafUfDRaSMP3sfQftjvoNSW0HgwabmhTjpPcOls SdzTS/Fd9EmXKaKTU2juCuj9EWBdqJP9pB4bDd8P0ynqISnzerkD2BjRY2o1ZBrWjH/5 eO8RIMur1xKNZWdcMME4DMZYG5LMsPWQROOH9LXcj8ms3E2NnhDjfSFM8VvFtLhiuemX gvrEADK+vxg/dvc9hgYZcVOkA75stEYcGhOizuNIZSARmYi6AL/UtOXlJyq+Gqic5ZEk EpGjI36MA9i6D5EOlysB2WBQZlUbcUqryyvbzArwRWd670xtWgqbQEfx9KhzQbj8ROO+ GyLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VP/AAyYjw0Rr7hmFWioIleiT2CT56Mt2aJdhU6I1hPs=; b=M3SsENQfHIZHJf5g0QgTkAK+poZnd/qH78aN9c7syCSPDqd8i29xy01UvDv/mLLjqe OcT6QXglTGPRnNEEpCLKhMalnifAIUsw+XnB/xixW6QVz0bFJzNkB0JsGi+B3hYjj2Vi JpD1FG0hI8dD2XaIbBUNJGjMYqVB+qEYvYjoiMgGVuAWdNG1UXEq679i9MJNpXooyYxa Cc+4k/dT0HKTxVai7c4juBFZs4lGkCstA+B3oIpUQxiJaS27PnPRjUah2yasOyrd8/el 2w0iSaxRuCyR2LHl1T75kRzTvGMO0wWtRrK0PqMyL+zN3ZrWPhF/ejMaRMHpjsTkgyHZ y/YQ== X-Gm-Message-State: ACrzQf0X3nQX23sqvSZ6bpxShDrX+txGHMTWyK1gdJR4R1g/2pLHXtpH jdTrWd3BM2GPO3BO63ewIxx04g== X-Google-Smtp-Source: AMsMyM79vGE5PFEjFAOVv+DbTOO0VPtPZm7r9D3PRR3cr5HMSyg3SrQP8NxQj9GCPzgkc6o6XfqqVA== X-Received: by 2002:a05:6512:ac8:b0:4a2:61e7:7963 with SMTP id n8-20020a0565120ac800b004a261e77963mr3501593lfu.363.1667145330088; Sun, 30 Oct 2022 08:55:30 -0700 (PDT) Received: from localhost.localdomain ([195.165.23.90]) by smtp.gmail.com with ESMTPSA id f4-20020ac24e44000000b00497a1f92a72sm842982lfr.221.2022.10.30.08.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 08:55:29 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong Subject: [PATCH v3 07/11] clk: qcom: mmcc-msm8974: move clock parent tables down Date: Sun, 30 Oct 2022 18:55:16 +0300 Message-Id: <20221030155520.91629-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221030155520.91629-1-dmitry.baryshkov@linaro.org> References: <20221030155520.91629-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move clock parent tables down, after the PLL declarataions, so that we can use pll hw clock fields in the next commit. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/mmcc-msm8974.c | 170 ++++++++++++++++---------------- 1 file changed, 85 insertions(+), 85 deletions(-) diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index 9008df2305df..57f1a351c8f6 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -42,6 +42,91 @@ enum { P_DSI1PLL_BYTE, }; +static struct clk_pll mmpll0 = { + .l_reg = 0x0004, + .m_reg = 0x0008, + .n_reg = 0x000c, + .config_reg = 0x0014, + .mode_reg = 0x0000, + .status_reg = 0x001c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll0", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap mmpll0_vote = { + .enable_reg = 0x0100, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "mmpll0_vote", + .parent_names = (const char *[]){ "mmpll0" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll mmpll1 = { + .l_reg = 0x0044, + .m_reg = 0x0048, + .n_reg = 0x004c, + .config_reg = 0x0050, + .mode_reg = 0x0040, + .status_reg = 0x005c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll1", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap mmpll1_vote = { + .enable_reg = 0x0100, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "mmpll1_vote", + .parent_names = (const char *[]){ "mmpll1" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static struct clk_pll mmpll2 = { + .l_reg = 0x4104, + .m_reg = 0x4108, + .n_reg = 0x410c, + .config_reg = 0x4110, + .mode_reg = 0x4100, + .status_reg = 0x411c, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll2", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_pll mmpll3 = { + .l_reg = 0x0084, + .m_reg = 0x0088, + .n_reg = 0x008c, + .config_reg = 0x0090, + .mode_reg = 0x0080, + .status_reg = 0x009c, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll3", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { { P_XO, 0 }, { P_MMPLL0, 1 }, @@ -160,91 +245,6 @@ static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { "dsi1pllbyte", }; -static struct clk_pll mmpll0 = { - .l_reg = 0x0004, - .m_reg = 0x0008, - .n_reg = 0x000c, - .config_reg = 0x0014, - .mode_reg = 0x0000, - .status_reg = 0x001c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mmpll0", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap mmpll0_vote = { - .enable_reg = 0x0100, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "mmpll0_vote", - .parent_names = (const char *[]){ "mmpll0" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll mmpll1 = { - .l_reg = 0x0044, - .m_reg = 0x0048, - .n_reg = 0x004c, - .config_reg = 0x0050, - .mode_reg = 0x0040, - .status_reg = 0x005c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mmpll1", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap mmpll1_vote = { - .enable_reg = 0x0100, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "mmpll1_vote", - .parent_names = (const char *[]){ "mmpll1" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - -static struct clk_pll mmpll2 = { - .l_reg = 0x4104, - .m_reg = 0x4108, - .n_reg = 0x410c, - .config_reg = 0x4110, - .mode_reg = 0x4100, - .status_reg = 0x411c, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mmpll2", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_pll mmpll3 = { - .l_reg = 0x0084, - .m_reg = 0x0088, - .n_reg = 0x008c, - .config_reg = 0x0090, - .mode_reg = 0x0080, - .status_reg = 0x009c, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "mmpll3", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - static struct clk_rcg2 mmss_ahb_clk_src = { .cmd_rcgr = 0x5000, .hid_width = 5,