| Message ID | 20221030155520.91629-7-dmitry.baryshkov@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: update MSM8974 clock controller drivers | expand |
On 30.10.2022 16:55, Dmitry Baryshkov wrote: > Use ARRAY_SIZE() instead of manually specifying num_parents. This makes > adding/removing entries to/from parent_data easy and errorproof. > > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > drivers/clk/qcom/mmcc-msm8974.c | 74 ++++++++++++++++----------------- > 1 file changed, 37 insertions(+), 37 deletions(-) > > diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c > index f74662925a58..9008df2305df 100644 > --- a/drivers/clk/qcom/mmcc-msm8974.c > +++ b/drivers/clk/qcom/mmcc-msm8974.c > @@ -252,7 +252,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "mmss_ahb_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -289,7 +289,7 @@ static struct clk_rcg2 mmss_axi_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "mmss_axi_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -313,7 +313,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "ocmemnoc_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -332,7 +332,7 @@ static struct clk_rcg2 csi0_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "csi0_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -345,7 +345,7 @@ static struct clk_rcg2 csi1_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "csi1_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -358,7 +358,7 @@ static struct clk_rcg2 csi2_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "csi2_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -371,7 +371,7 @@ static struct clk_rcg2 csi3_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "csi3_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -418,7 +418,7 @@ static struct clk_rcg2 vfe0_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "vfe0_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -431,7 +431,7 @@ static struct clk_rcg2 vfe1_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "vfe1_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -472,7 +472,7 @@ static struct clk_rcg2 mdp_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "mdp_clk_src", > .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, > - .num_parents = 6, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -495,7 +495,7 @@ static struct clk_rcg2 jpeg0_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "jpeg0_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -508,7 +508,7 @@ static struct clk_rcg2 jpeg1_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "jpeg1_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -521,7 +521,7 @@ static struct clk_rcg2 jpeg2_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "jpeg2_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -534,7 +534,7 @@ static struct clk_rcg2 pclk0_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "pclk0_clk_src", > .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, > - .num_parents = 6, > + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), > .ops = &clk_pixel_ops, > .flags = CLK_SET_RATE_PARENT, > }, > @@ -548,7 +548,7 @@ static struct clk_rcg2 pclk1_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "pclk1_clk_src", > .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, > - .num_parents = 6, > + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), > .ops = &clk_pixel_ops, > .flags = CLK_SET_RATE_PARENT, > }, > @@ -581,7 +581,7 @@ static struct clk_rcg2 vcodec0_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "vcodec0_clk_src", > .parent_names = mmcc_xo_mmpll0_1_3_gpll0, > - .num_parents = 5, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -599,7 +599,7 @@ static struct clk_rcg2 cci_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "cci_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -623,7 +623,7 @@ static struct clk_rcg2 camss_gp0_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "camss_gp0_clk_src", > .parent_names = mmcc_xo_mmpll0_1_gpll1_0, > - .num_parents = 5, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -637,7 +637,7 @@ static struct clk_rcg2 camss_gp1_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "camss_gp1_clk_src", > .parent_names = mmcc_xo_mmpll0_1_gpll1_0, > - .num_parents = 5, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -672,7 +672,7 @@ static struct clk_rcg2 mclk0_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "mclk0_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -685,7 +685,7 @@ static struct clk_rcg2 mclk1_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "mclk1_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -698,7 +698,7 @@ static struct clk_rcg2 mclk2_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "mclk2_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -711,7 +711,7 @@ static struct clk_rcg2 mclk3_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "mclk3_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -730,7 +730,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "csi0phytimer_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -743,7 +743,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "csi1phytimer_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -756,7 +756,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "csi2phytimer_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -787,7 +787,7 @@ static struct clk_rcg2 cpp_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "cpp_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -805,7 +805,7 @@ static struct clk_rcg2 byte0_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "byte0_clk_src", > .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, > - .num_parents = 6, > + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), > .ops = &clk_byte2_ops, > .flags = CLK_SET_RATE_PARENT, > }, > @@ -819,7 +819,7 @@ static struct clk_rcg2 byte1_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "byte1_clk_src", > .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, > - .num_parents = 6, > + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), > .ops = &clk_byte2_ops, > .flags = CLK_SET_RATE_PARENT, > }, > @@ -838,7 +838,7 @@ static struct clk_rcg2 edpaux_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "edpaux_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -857,7 +857,7 @@ static struct clk_rcg2 edplink_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "edplink_clk_src", > .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, > - .num_parents = 6, > + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), > .ops = &clk_rcg2_ops, > .flags = CLK_SET_RATE_PARENT, > }, > @@ -877,7 +877,7 @@ static struct clk_rcg2 edppixel_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "edppixel_clk_src", > .parent_names = mmcc_xo_dsi_hdmi_edp, > - .num_parents = 6, > + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp), > .ops = &clk_edp_pixel_ops, > }, > }; > @@ -895,7 +895,7 @@ static struct clk_rcg2 esc0_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "esc0_clk_src", > .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, > - .num_parents = 6, > + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -908,7 +908,7 @@ static struct clk_rcg2 esc1_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "esc1_clk_src", > .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, > - .num_parents = 6, > + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -926,7 +926,7 @@ static struct clk_rcg2 extpclk_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "extpclk_clk_src", > .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, > - .num_parents = 6, > + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), > .ops = &clk_byte_ops, > .flags = CLK_SET_RATE_PARENT, > }, > @@ -945,7 +945,7 @@ static struct clk_rcg2 hdmi_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "hdmi_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -963,7 +963,7 @@ static struct clk_rcg2 vsync_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "vsync_clk_src", > .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, > - .num_parents = 4, > + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), > .ops = &clk_rcg2_ops, > }, > };
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c index f74662925a58..9008df2305df 100644 --- a/drivers/clk/qcom/mmcc-msm8974.c +++ b/drivers/clk/qcom/mmcc-msm8974.c @@ -252,7 +252,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mmss_ahb_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -289,7 +289,7 @@ static struct clk_rcg2 mmss_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mmss_axi_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -313,7 +313,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "ocmemnoc_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -332,7 +332,7 @@ static struct clk_rcg2 csi0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -345,7 +345,7 @@ static struct clk_rcg2 csi1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -358,7 +358,7 @@ static struct clk_rcg2 csi2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi2_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -371,7 +371,7 @@ static struct clk_rcg2 csi3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi3_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -418,7 +418,7 @@ static struct clk_rcg2 vfe0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vfe0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -431,7 +431,7 @@ static struct clk_rcg2 vfe1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vfe1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -472,7 +472,7 @@ static struct clk_rcg2 mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -495,7 +495,7 @@ static struct clk_rcg2 jpeg0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -508,7 +508,7 @@ static struct clk_rcg2 jpeg1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -521,7 +521,7 @@ static struct clk_rcg2 jpeg2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "jpeg2_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -534,7 +534,7 @@ static struct clk_rcg2 pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -548,7 +548,7 @@ static struct clk_rcg2 pclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk1_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_pixel_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -581,7 +581,7 @@ static struct clk_rcg2 vcodec0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vcodec0_clk_src", .parent_names = mmcc_xo_mmpll0_1_3_gpll0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -599,7 +599,7 @@ static struct clk_rcg2 cci_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cci_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -623,7 +623,7 @@ static struct clk_rcg2 camss_gp0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp0_clk_src", .parent_names = mmcc_xo_mmpll0_1_gpll1_0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0), .ops = &clk_rcg2_ops, }, }; @@ -637,7 +637,7 @@ static struct clk_rcg2 camss_gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "camss_gp1_clk_src", .parent_names = mmcc_xo_mmpll0_1_gpll1_0, - .num_parents = 5, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_gpll1_0), .ops = &clk_rcg2_ops, }, }; @@ -672,7 +672,7 @@ static struct clk_rcg2 mclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk0_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -685,7 +685,7 @@ static struct clk_rcg2 mclk1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk1_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -698,7 +698,7 @@ static struct clk_rcg2 mclk2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk2_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -711,7 +711,7 @@ static struct clk_rcg2 mclk3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mclk3_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -730,7 +730,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi0phytimer_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -743,7 +743,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi1phytimer_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -756,7 +756,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "csi2phytimer_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -787,7 +787,7 @@ static struct clk_rcg2 cpp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "cpp_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -805,7 +805,7 @@ static struct clk_rcg2 byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -819,7 +819,7 @@ static struct clk_rcg2 byte1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte1_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_byte2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -838,7 +838,7 @@ static struct clk_rcg2 edpaux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "edpaux_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -857,7 +857,7 @@ static struct clk_rcg2 edplink_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "edplink_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -877,7 +877,7 @@ static struct clk_rcg2 edppixel_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "edppixel_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp), .ops = &clk_edp_pixel_ops, }, }; @@ -895,7 +895,7 @@ static struct clk_rcg2 esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -908,7 +908,7 @@ static struct clk_rcg2 esc1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc1_clk_src", .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -926,7 +926,7 @@ static struct clk_rcg2 extpclk_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "extpclk_clk_src", .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0, - .num_parents = 6, + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0), .ops = &clk_byte_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -945,7 +945,7 @@ static struct clk_rcg2 hdmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -963,7 +963,7 @@ static struct clk_rcg2 vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0, - .num_parents = 4, + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0), .ops = &clk_rcg2_ops, }, };