From patchwork Sun Oct 30 15:55:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 620096 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71DB4FA374B for ; Sun, 30 Oct 2022 15:55:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229544AbiJ3Pzb (ORCPT ); Sun, 30 Oct 2022 11:55:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229695AbiJ3Pza (ORCPT ); Sun, 30 Oct 2022 11:55:30 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2EB9D5B for ; Sun, 30 Oct 2022 08:55:28 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id z24so14118711ljn.4 for ; Sun, 30 Oct 2022 08:55:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a4b3VDC5du5iio3wMznYg7ulqmdVJGK4H8IaPURNvGQ=; b=m/lKYAevAKU9h7hlPA/pUvsf8tshU3aCAwwVeLCM3Q5U4JEnwjRzBMSyT+WaoI0mX9 VnKJb7bo9VQYhqbKFsi+wE/5wD0aeKkXtnjfUVJwxcvLZbiNne9WITiAb5q1TaUKz8XG YdBom7zs4Qq5cksk0Jg6co3kePBq+GYzD7EcDr4i7p0zKHxU9/rK33KRgG/xXSI+HE1b MuWXYdVK6cslGEwzGGyAfzwU1QVqFGxFwnVo4BPPJWJA4D6ppoiPG/gbnDiUaJxYo2sY wvP3sJljloVfRTc2hjd53FgLNTGkBJoUCyBAhcGX3nzGQV2EBNE4WK3mX4K5Hg95Afo0 BCJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a4b3VDC5du5iio3wMznYg7ulqmdVJGK4H8IaPURNvGQ=; b=xYJGTRQbyos8UxCb0x07fEBPvEsRhE4vbSZKXUxoReECPq1ZavzBDnbSH+Dngtay6B Z5ARehqNNoG3gxIXbw2LPHZK8RLDVPXOxG5B9I2ioihaOnfqlyPfWtaGDgFH4hrqk+1+ BI8U3p/mBVTrIIpJ1ErAk0hqUPK5x1Z0X2AZopnEEJ5utW7oY8lRnJTN568+EW3Yj2/V FIdDQy+oMEcvXhAXXAvv7yeo85qyrMZeAREDjfeyxoB+cYecnu8dARRsjes6kdp8novO Gid4DfNE7Y/YhGgxunaq0AEUhs/IebN0N3vNiZ7P4BrjfmL3mGLZY8OIkuGHMPd37SW1 a8ZA== X-Gm-Message-State: ACrzQf21BJgaR28HFX6uorQlMmXip8UYSUb0rDK3c3g4sAaCuPwrFWa8 g9YySBkCa0mzCN0GRNgtmnFwpw== X-Google-Smtp-Source: AMsMyM6+7wnYu4mqedwKw61PRdaJBs1gdyAjeREmzz9DDnrqA7cSS0hN9USGTHlkTzLF+UuXDTg5OQ== X-Received: by 2002:a2e:8793:0:b0:277:4b8:192f with SMTP id n19-20020a2e8793000000b0027704b8192fmr3495093lji.442.1667145327300; Sun, 30 Oct 2022 08:55:27 -0700 (PDT) Received: from localhost.localdomain ([195.165.23.90]) by smtp.gmail.com with ESMTPSA id f4-20020ac24e44000000b00497a1f92a72sm842982lfr.221.2022.10.30.08.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 08:55:27 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong Subject: [PATCH v3 04/11] clk: qcom: gcc-msm8974: move clock parent tables down Date: Sun, 30 Oct 2022 18:55:13 +0300 Message-Id: <20221030155520.91629-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221030155520.91629-1-dmitry.baryshkov@linaro.org> References: <20221030155520.91629-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rearrage clock parent tables and PLL declarations (pull parents down and gpll4 up), so that we can use pll hw clock fields in the next commit. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-msm8974.c | 98 +++++++++++++++++----------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index b847ce852ef8..77f3497265a0 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -32,28 +32,6 @@ enum { P_GPLL4, }; -static const struct parent_map gcc_xo_gpll0_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 } -}; - -static const char * const gcc_xo_gpll0[] = { - "xo", - "gpll0_vote", -}; - -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL4, 5 } -}; - -static const char * const gcc_xo_gpll0_gpll4[] = { - "xo", - "gpll0_vote", - "gpll4_vote", -}; - static struct clk_pll gpll0 = { .l_reg = 0x0004, .m_reg = 0x0008, @@ -81,6 +59,55 @@ static struct clk_regmap gpll0_vote = { }, }; +static struct clk_pll gpll4 = { + .l_reg = 0x1dc4, + .m_reg = 0x1dc8, + .n_reg = 0x1dcc, + .config_reg = 0x1dd4, + .mode_reg = 0x1dc0, + .status_reg = 0x1ddc, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll4", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll4_vote = { + .enable_reg = 0x1480, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_vote", + .parent_names = (const char *[]){ "gpll4" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + +static const struct parent_map gcc_xo_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 } +}; + +static const char * const gcc_xo_gpll0[] = { + "xo", + "gpll0_vote", +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL4, 5 } +}; + +static const char * const gcc_xo_gpll0_gpll4[] = { + "xo", + "gpll0_vote", + "gpll4_vote", +}; + static struct clk_rcg2 config_noc_clk_src = { .cmd_rcgr = 0x0150, .hid_width = 5, @@ -144,33 +171,6 @@ static struct clk_regmap gpll1_vote = { }, }; -static struct clk_pll gpll4 = { - .l_reg = 0x1dc4, - .m_reg = 0x1dc8, - .n_reg = 0x1dcc, - .config_reg = 0x1dd4, - .mode_reg = 0x1dc0, - .status_reg = 0x1ddc, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll4", - .parent_names = (const char *[]){ "xo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll4_vote = { - .enable_reg = 0x1480, - .enable_mask = BIT(4), - .hw.init = &(struct clk_init_data){ - .name = "gpll4_vote", - .parent_names = (const char *[]){ "gpll4" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = { F(125000000, P_GPLL0, 1, 5, 24), { }