From patchwork Tue Oct 18 21:15:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 616159 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97C0DC4332F for ; Tue, 18 Oct 2022 21:15:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230283AbiJRVPu (ORCPT ); Tue, 18 Oct 2022 17:15:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230230AbiJRVPq (ORCPT ); Tue, 18 Oct 2022 17:15:46 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 695B28E0FF; Tue, 18 Oct 2022 14:15:45 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29ILFcuk079163; Tue, 18 Oct 2022 16:15:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666127738; bh=SzSCIjFSyDevJ5u2FZeVzuQFI/im3txyQBcW8fq5/iM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=m3f4mup663uL58iMdRIVGWe5hjK0NrbxzbrvvKLnb0TAnR/OWm5qi9MJQe9wP3Uae sit/3R+eSEQnWSO1YKadJnk9OaN5dXzCVPp3qxa+g57A+XzEXQ7AewBrSU13DEQuB5 +S1XoEBdJ10CNCua5sqe+dC0JAs4TgbGdfXFLpyU= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29ILFbnu014783 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 18 Oct 2022 16:15:38 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 18 Oct 2022 16:15:37 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 18 Oct 2022 16:15:37 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29ILFXoG014456; Tue, 18 Oct 2022 16:15:37 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , , , CC: Andrew Davis Subject: [PATCH 06/10] arm64: dts: ti: k3-am62: MDIO pinmux should belong to the MDIO node Date: Tue, 18 Oct 2022 16:15:29 -0500 Message-ID: <20221018211533.21335-7-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221018211533.21335-1-afd@ti.com> References: <20221018211533.21335-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Although usually integrated as a child of an Ethernet controller, MDIO IP has an independent pinout. This pinout should be controlled by the MDIO node (so if it was to be disabled for instance, the pinmux state would reflect that). Move the MDIO pins pinmux to the MIDO nodes. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 197d329a6082..318ec805ff54 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -353,8 +353,7 @@ &sdhci1 { &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&main_mdio1_pins_default - &main_rgmii1_pins_default + pinctrl-0 = <&main_rgmii1_pins_default &main_rgmii2_pins_default>; }; @@ -369,6 +368,9 @@ &cpsw_port2 { }; &cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ;