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Tue, 11 Oct 2022 01:20:51 -0500 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Tue, 11 Oct 2022 01:20:48 -0500 From: Amit Kumar Mahapatra To: , , CC: , , , , , , Amit Kumar Mahapatra Subject: [PATCH v4 2/7] spi: spi-zynqmp-gqspi: Set CPOL and CPHA during hardware init Date: Tue, 11 Oct 2022 11:50:35 +0530 Message-ID: <20221011062040.12116-3-amit.kumar-mahapatra@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221011062040.12116-1-amit.kumar-mahapatra@amd.com> References: <20221011062040.12116-1-amit.kumar-mahapatra@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT004:EE_|SA0PR12MB4542:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c6444a2-7da2-4963-2db6-08daab50c25e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: j8IVbn0ATNGaMX5/4SfthfLTaSTGx38JXx7gat1WV+808SMvFGqRLgPvWpzrtp8yJHAYvp+t6GvI9VjtZyiVwL4UDS6w3pfzdrUTqSEHQK/f0h1QWGR3Rgszs5qsRepSLwDpY6HZSAnlsCSxCcJnLZoO1ZAmp3rQxx8cZhjRMpMSaEouYdIUzbyVGZ4WqFYaQVZQvyx4n6GkO2xlnEgKXjMENryABD4sRpbhztgU1x0TR7TuycEj8iRacZEXXp6t8mWfBW3M2aoRlBP7odoBd099u5dI8KKoBHqLkYscPn5W0/hutN6cr4ccUtmGAtVgKE6Bz/h7csGKXCYWzc0B/jUsYaoqkNo9Wz7mhQYefD8vLZKrs4Z5UmhiE1IoBi1IaMqVshTcbAoRI3Kmdrnkv2232EEUQcsPl0dYN6u9G+m1o4zrFkBGa9fgo6K8yQuqAy7BAjxOw4IZEie575eDRIT19RGh7omxsAYaiLlrcLjlv45ANuUIrqAKr3zmG/MonnJasf573/DBlw5n66VLymzbGeOM5jP1Dyfl94kzG2ElevWOyMX+s+Eqvabj68+Npbvh5joWWO2HHlVgovyzTi5DH/LpBBGdk4ZlgjMBrk0jejA4BPH145WA6dNKMsHy6pUhUHCAAcDXMeOLoOkobDsuhZ7K+XMr7IUJ7WtNcT6CX1LzFPKwoEZxh9h0K+H0PxXOxFVVnbu3sbVUvEcCfe6uGmB4jed2A9ntmTPodZbDiBD0PQnYn605fkStlA5RnpW/Oi6MWgJ+Yj4WyFn6g10zCdmAeafE4HvBV1cHL460VYxciSqN1MkXq/BrOBys X-Forefront-Antispam-Report: CIP:165.204.84.17; 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But the CPOL & CPHA values do not change in between multiple transfers, so moved the CPOL & CPHA initialization to hardware init so that the values are written only once. Signed-off-by: Amit Kumar Mahapatra --- drivers/spi/spi-zynqmp-gqspi.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 973008a30a09..1b56dd29057f 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -266,7 +266,9 @@ static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr, * - Enable manual slave select * - Enable manual start * - Deselect all the chip select lines - * - Set the little endian mode of TX FIFO and + * - Set the little endian mode of TX FIFO + * - Set clock phase + * - Set clock polarity and * - Enable the QSPI controller */ static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) @@ -305,10 +307,17 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) config_reg |= GQSPI_CFG_WP_HOLD_MASK; /* Clear pre-scalar by default */ config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; - /* CPHA 0 */ - config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; - /* CPOL 0 */ - config_reg &= ~GQSPI_CFG_CLK_POL_MASK; + /* Set CPHA */ + if (xqspi->ctlr->mode_bits & SPI_CPHA) + config_reg |= GQSPI_CFG_CLK_PHA_MASK; + else + config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; + /* Set CPOL */ + if (xqspi->ctlr->mode_bits & SPI_CPOL) + config_reg |= GQSPI_CFG_CLK_POL_MASK; + else + config_reg &= ~GQSPI_CFG_CLK_POL_MASK; + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); /* Clear the TX and RX FIFO */ @@ -470,14 +479,6 @@ static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); - /* Set the QSPI clock phase and clock polarity */ - config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK); - - if (qspi->mode & SPI_CPHA) - config_reg |= GQSPI_CFG_CLK_PHA_MASK; - if (qspi->mode & SPI_CPOL) - config_reg |= GQSPI_CFG_CLK_POL_MASK; - config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT); zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); @@ -1170,6 +1171,9 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) goto clk_dis_all; } + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | + SPI_TX_DUAL | SPI_TX_QUAD; + /* QSPI controller initializations */ zynqmp_qspi_init_hw(xqspi); @@ -1207,8 +1211,6 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) ctlr->setup = zynqmp_qspi_setup_op; ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; ctlr->bits_per_word_mask = SPI_BPW_MASK(8); - ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; ctlr->dev.of_node = np; ctlr->auto_runtime_pm = true;