From patchwork Fri Oct 7 12:59:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 613231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DD2EC43219 for ; Fri, 7 Oct 2022 13:00:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229783AbiJGM76 (ORCPT ); Fri, 7 Oct 2022 08:59:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229796AbiJGM7t (ORCPT ); Fri, 7 Oct 2022 08:59:49 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6878910043; Fri, 7 Oct 2022 05:59:46 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id a10so7167785wrm.12; Fri, 07 Oct 2022 05:59:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9vClqKApfyGN9WzsedjcjkB/+ulaVGv1bqzEz0Uo9bA=; b=ASUgrTh6DB3VaMfJlUJuqLjw2D1zFeGIoccRQNKlJjGs3DuKXGpfRKreYm9HbEXFOO WLWP6xugIDUsgZ3VpOdclSMgmMFyeDpNHAgsgZoGvocALx5MVCRgeAvmDaD72d48oP54 YiWGlJLUPQffPPZCeu1pkS24OE+zFyaBIN5gWsU4taIyv8b+Cn5zQBx4cK+vZbq9Iwji oSjIqXq/aSyeDZz6L2aBHgftxcXIxyvC61BmhuSagj1JAzTnS0+hPri01IFl1ghq22lW d2+Vzk/0ih1kvfxqjJ1oIWtV8yU1Y0J/sDeCATt1WR2/+SA8wxhpquDz0hn7gx9SSNp8 WyNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9vClqKApfyGN9WzsedjcjkB/+ulaVGv1bqzEz0Uo9bA=; b=krilm4ZFQ8xanlCaImlfT2SdkPG2fl3n3TZ7J+eoh9ob1+zSIhV4cphnVz1LHk0kwi +eA+sUiihjrDZoDmNcMgUrsFCrqbv+VTFHQnvgqrpMsXB6s2HMo2ceel6BfX9+IHAFP+ Kmn+/HR5JZOkg6rKXJind/wcjcRzW110WDnLxSEx7uOVc3JiF+ARAf7BkVgHOJsCGCqO oaZGnq9y6XB7pyJugyzV9mIiNZgjPuQmPXp/02+8VxEgcwLgNBh3vlC5A21BG649bHfN dJJG4+lZ5CCIbQ00Liw6QIDc77+n+fcqF+FNw93J8HH8IatT59dfv8NuOBbFEvCtC8wu HRyQ== X-Gm-Message-State: ACrzQf1APHfOeRjF3TvTJOlSG/KXS8QgrbhZL76Z3nTczDLpdIGHhASm 6DPP7xFz4FEeR8mRGON0ifM= X-Google-Smtp-Source: AMsMyM5RbkucakUi/gK1HIiZaokX0zCNmCXgLPqeS4Ph06ZdQMQd7RSnYJhlYRkE0NMjygDqnLpapg== X-Received: by 2002:a5d:6547:0:b0:22e:465c:6d14 with SMTP id z7-20020a5d6547000000b0022e465c6d14mr3136800wrv.208.1665147585623; Fri, 07 Oct 2022 05:59:45 -0700 (PDT) Received: from localhost.localdomain ([95.183.227.98]) by smtp.gmail.com with ESMTPSA id i15-20020adffdcf000000b00223b8168b15sm2008243wrs.66.2022.10.07.05.59.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Oct 2022 05:59:45 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Andy Teng , AngeloGioacchino Del Regno Cc: Yassine Oudjana , Yassine Oudjana , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 06/10] dt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add MT6795 Date: Fri, 7 Oct 2022 15:59:00 +0300 Message-Id: <20221007125904.55371-7-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221007125904.55371-1-y.oudjana@protonmail.com> References: <20221007125904.55371-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Yassine Oudjana Combine MT6795 pin controller document into MT6779 one. In the process, replace the current interrupts property description with the one from the MT6795 document since it makes more sense. Also amend property descriptions and examples with more detailed information that was available in the MT6795 document, and replace the current pinmux node name patterns with ones from it since they are more common across mediatek pin controller bindings. Signed-off-by: Yassine Oudjana --- .../pinctrl/mediatek,mt6779-pinctrl.yaml | 94 ++++++-- .../pinctrl/mediatek,pinctrl-mt6795.yaml | 227 ------------------ 2 files changed, 77 insertions(+), 244 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index a2141eb0854e..cada3530dd0a 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -8,6 +8,7 @@ title: Mediatek MT6779 Pin Controller maintainers: - Andy Teng + - AngeloGioacchino Del Regno - Sean Wang description: @@ -18,6 +19,7 @@ properties: compatible: enum: - mediatek,mt6779-pinctrl + - mediatek,mt6795-pinctrl - mediatek,mt6797-pinctrl reg: @@ -43,9 +45,10 @@ properties: interrupt-controller: true interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 description: | - Specifies the summary IRQ. + The interrupt outputs to sysirq. "#interrupt-cells": const: 2 @@ -81,6 +84,30 @@ allOf: - const: iocfg_lt - const: iocfg_tl - const: eint + + interrupts: + items: + - description: EINT interrupt + + - if: + properties: + compatible: + contains: + const: mediatek,mt6795-pinctrl + then: + properties: + reg: + minItems: 2 + + reg-names: + items: + - const: base + - const: eint + + interrupts: + items: + - description: EINT interrupt + - description: EINT event_b interrupt - if: properties: compatible: @@ -111,32 +138,50 @@ allOf: - "#interrupt-cells" patternProperties: - '-[0-9]*$': + '-pins$': type: object additionalProperties: false patternProperties: - '-pins*$': + '^pins': type: object description: | A pinctrl node should contain at least one subnodes representing the pinctrl groups available on the machine. Each subnode will list the pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and input schmitt. - $ref: "/schemas/pinctrl/pincfg-node.yaml" + configuration, pullups, drive strength, input enable/disable and + input schmitt. + $ref: "pinmux-node.yaml" properties: pinmux: description: - integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined - as macros in boot/dts/-pinfunc.h directly. + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/-pinfunc.h + directly. bias-disable: true - bias-pull-up: true - - bias-pull-down: true + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: Pull up PUPD/R0/R1 type define value. + description: | + For normal pull up type, it is not necessary to specify R1R0 + values; When pull up type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: Pull down PUPD/R0/R1 type define value. + description: | + For normal pull down type, it is not necessary to specify R1R0 + values; When pull down type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. input-enable: true @@ -151,7 +196,7 @@ patternProperties: input-schmitt-disable: true drive-strength: - enum: [2, 4, 8, 12, 16] + enum: [2, 4, 6, 8, 10, 12, 14, 16] slew-rate: enum: [0, 1] @@ -218,8 +263,9 @@ examples: #interrupt-cells = <2>; interrupts = ; - mmc0_pins_default: mmc0-0 { - cmd-dat-pins { + /* GPIOs 167-174, 176-178 set as multifunction MSDC0 */ + mmc0_pins_default: mmc0-pins { + pins-cmd-dat { pinmux = , , , @@ -232,15 +278,29 @@ examples: input-enable; mediatek,pull-up-adv = <1>; }; - clk-pins { + pins-clk { pinmux = ; mediatek,pull-down-adv = <2>; }; - rst-pins { + pins-rst { pinmux = ; mediatek,pull-up-adv = <0>; }; }; + + /* GPIO0 set as multifunction GPIO0 */ + gpio-pins { + pins { + pinmux = ; + }; + }; + + /* GPIO52 set as multifunction SDA0 */ + i2c0-pins { + pins { + pinmux = ; + }; + }; }; mmc0 { diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml deleted file mode 100644 index a3a3f7fb9605..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml +++ /dev/null @@ -1,227 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Mediatek MT6795 Pin Controller - -maintainers: - - AngeloGioacchino Del Regno - - Sean Wang - -description: | - The Mediatek's Pin controller is used to control SoC pins. - -properties: - compatible: - const: mediatek,mt6795-pinctrl - - gpio-controller: true - - '#gpio-cells': - description: | - Number of cells in GPIO specifier. Since the generic GPIO binding is used, - the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. - const: 2 - - gpio-ranges: - description: GPIO valid number range. - maxItems: 1 - - reg: - description: - Physical address base for gpio base and eint registers. - minItems: 2 - - reg-names: - items: - - const: base - - const: eint - - interrupt-controller: true - - '#interrupt-cells': - const: 2 - - interrupts: - description: The interrupt outputs to sysirq. - minItems: 1 - items: - - description: EINT interrupt - - description: EINT event_b interrupt - -# PIN CONFIGURATION NODES -patternProperties: - '-pins$': - type: object - additionalProperties: false - patternProperties: - '^pins': - type: object - additionalProperties: false - description: | - A pinctrl node should contain at least one subnodes representing the - pinctrl groups available on the machine. Each subnode will list the - pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. - An example of using macro: - pincontroller { - /* GPIO0 set as multifunction GPIO0 */ - gpio-pins { - pins { - pinmux = ; - } - }; - /* GPIO45 set as multifunction SDA0 */ - i2c0-pins { - pins { - pinmux = ; - } - }; - }; - $ref: "pinmux-node.yaml" - - properties: - pinmux: - description: | - Integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are - defined as macros in dt-bindings/pinctrl/-pinfunc.h - directly. - - drive-strength: - enum: [2, 4, 6, 8, 10, 12, 14, 16] - - bias-pull-down: - oneOf: - - type: boolean - - enum: [100, 101, 102, 103] - description: mt6795 pull down PUPD/R0/R1 type define value. - description: | - For normal pull down type, it is not necessary to specify R1R0 - values; When pull down type is PUPD/R0/R1, adding R1R0 defines - will set different resistance values. - - bias-pull-up: - oneOf: - - type: boolean - - enum: [100, 101, 102, 103] - description: mt6795 pull up PUPD/R0/R1 type define value. - description: | - For normal pull up type, it is not necessary to specify R1R0 - values; When pull up type is PUPD/R0/R1, adding R1R0 defines - will set different resistance values. - - bias-disable: true - - output-high: true - - output-low: true - - input-enable: true - - input-disable: true - - input-schmitt-enable: true - - input-schmitt-disable: true - - mediatek,pull-up-adv: - description: | - Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: - 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. - 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. - 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. - 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] - - mediatek,pull-down-adv: - description: | - Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: - 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. - 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. - 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. - 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] - - required: - - pinmux - -allOf: - - $ref: "pinctrl.yaml#" - -required: - - compatible - - reg - - reg-names - - interrupts - - interrupt-controller - - '#interrupt-cells' - - gpio-controller - - '#gpio-cells' - - gpio-ranges - -additionalProperties: false - -examples: - - | - #include - #include - #include - - soc { - #address-cells = <2>; - #size-cells = <2>; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt6795-pinctrl"; - reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; - reg-names = "base", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 196>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <2>; - - i2c0-pins { - pins-sda-scl { - pinmux = , - ; - }; - }; - - mmc0-pins { - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - bias-pull-up = ; - }; - - pins-clk { - pinmux = ; - bias-pull-down = ; - }; - - pins-rst { - pinmux = ; - bias-pull-up = ; - }; - }; - }; - };