From patchwork Fri Oct 7 11:35:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 613586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42BBFC433F5 for ; Fri, 7 Oct 2022 11:35:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229582AbiJGLfu (ORCPT ); Fri, 7 Oct 2022 07:35:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229747AbiJGLft (ORCPT ); Fri, 7 Oct 2022 07:35:49 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A51BDC90C2; Fri, 7 Oct 2022 04:35:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1665142548; x=1696678548; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MHG2thRoVjC0ho07WGF50KRaA5/RfSwJFArrPBDrMJ4=; b=Rn07sl5YzfG0je2QR/v0OV7fgOkU79/P8EDGwAqcgjQ6LhY0Mq9MJG6T M5QATJYWK3sw2Ia8ekIstdIOFD+O5nvK76jGGCUYC5TQwOpUN2hm36bOz cJFf89aysdDdlzrsszy1PSCyfL60Pr78hcDvFP+OziteFSB4ubWYX1VM5 7/jCDiuOE55gi265iKkHC5FX+Y5Q4uB/ciehqsbvckR03E3QaGDXPP9ko s6ntmNN+85mTAsqpuQD2M9WY67DmT81LjHSdgmLfi36XOf+ClxlDK8x6H kGRxhYNpmKDk+fSE1dWoNVcQeCK935/6GUjoivVuF8pI7s0K8mXAkvwr0 A==; X-IronPort-AV: E=Sophos;i="5.95,166,1661842800"; d="scan'208";a="177501339" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 07 Oct 2022 04:35:48 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Fri, 7 Oct 2022 04:35:44 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Fri, 7 Oct 2022 04:35:42 -0700 From: Conor Dooley To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6n?= =?utf-8?q?ig?= , "Rob Herring" , Krzysztof Kozlowski CC: Daire McNamara , , , , , Conor Dooley , Rob Herring Subject: [PATCH v11 1/4] dt-bindings: pwm: fix microchip corePWM's pwm-cells Date: Fri, 7 Oct 2022 12:35:10 +0100 Message-ID: <20221007113512.91501-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221007113512.91501-1-conor.dooley@microchip.com> References: <20221007113512.91501-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org corePWM is capable of inverted operation but the binding requires \#pwm-cells of 2. Expand the binding to support setting the polarity. Fixes: df77f7735786 ("dt-bindings: pwm: add microchip corepwm binding") Acked-by: Rob Herring Acked-by: Uwe Kleine-König Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml index a7fae1772a81..cd8e9a8907f8 100644 --- a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml +++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml @@ -30,7 +30,9 @@ properties: maxItems: 1 "#pwm-cells": - const: 2 + enum: [2, 3] + description: + The only flag supported by the controller is PWM_POLARITY_INVERTED. microchip,sync-update-mask: description: |