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Miller" , Vladimir Oltean , Florian Fainelli , Vivien Didelot , Andrew Lunn Subject: [PATCH v2 net-next 11/14] mfd: ocelot: add regmaps for ocelot_ext Date: Wed, 21 Sep 2022 21:00:59 -0700 Message-Id: <20220922040102.1554459-12-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220922040102.1554459-1-colin.foster@in-advantage.com> References: <20220922040102.1554459-1-colin.foster@in-advantage.com> X-ClientProxiedBy: BYAPR05CA0009.namprd05.prod.outlook.com (2603:10b6:a03:c0::22) To DM5PR1001MB2345.namprd10.prod.outlook.com (2603:10b6:4:2d::31) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM5PR1001MB2345:EE_|SA2PR10MB4412:EE_ X-MS-Office365-Filtering-Correlation-Id: e2ee67d6-5b1a-4509-3587-08da9c4f24e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FVGXIeXMZJn63RY3+tHPZtOhkb3RbrJFdyBXzApeI4Bb3cxOsLgdXf8n/uvHuEkPJVKo3P4XHw6MqP1fWs7mRyl6O7h7/FtaBjpdwMnto39mUNqxv+ZOHXq2BumAzN+Jo00J7l/S2nIXT6ABPUMihij14fJZzWt3HczVQKYiKHvMAFOmiXGyhENP209cmJiKk52oedzUsDAwquIwknQnZxTHUxqZ2kxubFr/eed4d14JU+ee5781YLe2f7hVv+oIZ9HfY3VWoQ0FKS9Qu7py7Rxca6jrOVVDU++aeZqZ4EtUGOwkBp1O+QpdS/EZpBH8RoHmCgmFO8X3haf+52XgHJED2wasxRtiNfRCbvd9juX7xQNlFt9KBgbc2brTlSw+GF/lEAoxvLBLpoL26wIgrnY0Ehwm0vbJX1CHHbSM1bHyUO2BSboYxJPH9ZFhIWlrAYIf3M85KUD2E+n4vSjL5s+Muq8t8bDWkGd2lKGMLQg4yPpmXgHZipB0cKrAKemhAIoocAZzxt8qG94JoPAT7W7b6Ein8QusWeuY/iCKnK/YSDJbJskdsgAVp3o9EoqiU9uCF41LoaDKh3SGV9SiDoJHuMpf3qGBpchiVl13j9YXjyXFaePivN9zXZMEdInK1RxCsGNugsNCby+fL3B1Fg7QLFBM0giYu0T+aqNH4VVubviWHz//UYDf7v1/B3Z1ZRI30uj0xPCiVm8Z9yW14iyjrJY/yXOIdNjlvwSRKXLAzw+PtQCEfrtz9Cl9RUsphMYnYbD7QkRQuCWYstVZFg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM5PR1001MB2345.namprd10.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230022)(366004)(376002)(396003)(346002)(136003)(39830400003)(451199015)(36756003)(6506007)(6666004)(52116002)(6512007)(26005)(86362001)(66476007)(66556008)(54906003)(4326008)(66946007)(41300700001)(8676002)(6486002)(38350700002)(38100700002)(2616005)(186003)(478600001)(1076003)(2906002)(316002)(5660300002)(7416002)(44832011)(8936002); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: U68AKxuW1oqG2eIg5wMKEAWLTCBU8vfXwq/PODQb763m1hpK9qYtjgVMY2u2uzpDZSbN4DOgcB4S2hOsOouOmUeBVLHYf7MI1DV6wwXk0edLFPkhoOpS8nGWuq7Kn7NmOMUVlTejk88VZy7/Ju+frY4g9H3dbbEGhvaTJZxh89lyF9d3OoO3er/LxHMCpsIndyYIXcEavpvnxfWmBcQzfpsRIp5w7NxQatvoooVz8dA6P1N/214eFAiwKjSjP16ONNTB/MH2NVA+BvuvirZ6FWmwtYxUEoCZFkNyGv5wPUWZa2marCFGFnvrHJA4IyNmbhiWPSha31n2qDBXgSXgkJXYSTnnGv0L/8c6OUNHx7q2Yd3mesC+I7XoBlDjw8ZeoEHfmU8KOlSSZ2+xcDCuZqR3fMgvbDnx0T5Y3aImicNckiEPtb5Z11QSjXrA9YTTuEnGCvgACc5jX7xUAVSd/eCuj3kwLk2+hP+6beofu3+NK/qQmay1s9TuK/UQ9/4DalESCEfpOBP5MiTNmW0C/zd+cKxdwi1rQuOzuDX1T/mOV9KhhMfPw/tvErvfTw1yYAYGwBTQVcxrEaFjAcCcFwEHAsznnaT+a20we5PuXA6JogbzdG1FEqnn+DjOSUPARU9kH2QqAt8giPYkitXGRWhWjpsdxezH2mBqTWYaXwOKynEQcahyd4ilEexZwkN4iI+fb4UwcmRq+oQhM8euOlOJVib4wEoXhsMJbTX+8yu53LnztIUX60fldTpBZ4kt2dYt+jTZqZyn+hikEIvTHtN/rvGO43ZoSttRSbT+3+AumNODqDVO8lhIEVP7jvVbPB251kjlTnwocwjLd79mNefovuzQq48Qfu/F7ZeOy1hcCggPj3uxius6Wb9kUURYrOqU1PWMuNzgpvWZ6hZ8IgdQsHKiJ4UO7sdW7wfszmG1r5zXbbGee+8/BTt/ibg2dJxkFr4ozw9ckky5sGDZwwX0197fKWf9DL2aAHdAER7DVjCBaiCTPr0Ld+p/LCobrx4KcBElp1l/AwXlxFSgxh1U/iIon2oyMwZ+Lcur8I707vQRiRVmH9l+C1NPzAXffC1n1HCB5lISBJec/FoAfyYIrcZeNGIiJZtKM2EK5T4vmsjn0WUPBkH9ZZvEy5pWq4S7yzdkubbUYEmUiYruk1f5aI2rgbz919MDZgA7exgISPXUoRXT8zGuklYzebB+J6wGR/8/5lzqVWcn3lPB1wJapQvvA1Z2eB765ogPdENDY/HIIHv/aWV1ZWa7QEPXJQVVReFGO3d+5DkNgcuhkRVAJk+7KoHQyC0qYJ9t0xcaD68aehN6Mwuz1OJ4+HhJKP3zITMKk2BYp6fjo/qUQKnvcnyBAa25BEIzwKlHMpneVyMpSbmyQVUk55SfxsCmz9/IWztw9EuHbW9+eEU+lj2mGmmqNGhivDESjh26M9WILYNTgUvIjouvlRcpPPfzaH85PNs/wmOlwxiEg98ebIfDPmloZnYIm/UGGrk0I2rnKtADuQUAzM6ecnfE/AtEOcuYuybA3/h3NLDymgtFRVrSihFukskW7ODWnLBhHI4iAMwJFNAp1hAGCddne4J3VZGVJqf9dJyW8oMyquC4VL1tqpuAXEkWjJsg+OzJ84g= X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: e2ee67d6-5b1a-4509-3587-08da9c4f24e0 X-MS-Exchange-CrossTenant-AuthSource: DM5PR1001MB2345.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2022 04:01:36.2619 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: C/komwOJpYQYXnxlFjHWxSBVh7LZnGR93nvwUtSeBarN2IA6F1ppq+jAU1dvnPLFj1ytvQCsvrTTiUE/WWZ9vQhDuohniTxzYlcMjYba3wk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR10MB4412 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Ocelot switch core driver relies heavily on a fixed array of resources for both ports and peripherals. This is in contrast to existing peripherals - pinctrl for example - which have a one-to-one mapping of driver <> resource. As such, these regmaps must be created differently so that enumeration-based offsets are preserved. Register the regmaps to the core MFD device unconditionally so they can be referenced by the Ocelot switch / Felix DSA systems. Signed-off-by: Colin Foster --- v2 * Alignment of variables broken out to a separate patch * Structs now correctly use EXPORT_SYMBOL* * Logic moved and comments added to clear up conditionals around vsc7512_target_io_res[i].start v1 from previous RFC: * New patch --- drivers/mfd/ocelot-core.c | 87 ++++++++++++++++++++++++++++++++++++++ include/linux/mfd/ocelot.h | 5 +++ 2 files changed, 92 insertions(+) diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c index 013e83173062..702555fbdcc5 100644 --- a/drivers/mfd/ocelot-core.c +++ b/drivers/mfd/ocelot-core.c @@ -45,6 +45,45 @@ #define VSC7512_SIO_CTRL_RES_START 0x710700f8 #define VSC7512_SIO_CTRL_RES_SIZE 0x00000100 +#define VSC7512_HSIO_RES_START 0x710d0000 +#define VSC7512_HSIO_RES_SIZE 0x00000128 + +#define VSC7512_ANA_RES_START 0x71880000 +#define VSC7512_ANA_RES_SIZE 0x00010000 + +#define VSC7512_QS_RES_START 0x71080000 +#define VSC7512_QS_RES_SIZE 0x00000100 + +#define VSC7512_QSYS_RES_START 0x71800000 +#define VSC7512_QSYS_RES_SIZE 0x00200000 + +#define VSC7512_REW_RES_START 0x71030000 +#define VSC7512_REW_RES_SIZE 0x00010000 + +#define VSC7512_SYS_RES_START 0x71010000 +#define VSC7512_SYS_RES_SIZE 0x00010000 + +#define VSC7512_S0_RES_START 0x71040000 +#define VSC7512_S1_RES_START 0x71050000 +#define VSC7512_S2_RES_START 0x71060000 +#define VSC7512_S_RES_SIZE 0x00000400 + +#define VSC7512_GCB_RES_START 0x71070000 +#define VSC7512_GCB_RES_SIZE 0x0000022c + +#define VSC7512_PORT_0_RES_START 0x711e0000 +#define VSC7512_PORT_1_RES_START 0x711f0000 +#define VSC7512_PORT_2_RES_START 0x71200000 +#define VSC7512_PORT_3_RES_START 0x71210000 +#define VSC7512_PORT_4_RES_START 0x71220000 +#define VSC7512_PORT_5_RES_START 0x71230000 +#define VSC7512_PORT_6_RES_START 0x71240000 +#define VSC7512_PORT_7_RES_START 0x71250000 +#define VSC7512_PORT_8_RES_START 0x71260000 +#define VSC7512_PORT_9_RES_START 0x71270000 +#define VSC7512_PORT_10_RES_START 0x71280000 +#define VSC7512_PORT_RES_SIZE 0x00010000 + #define VSC7512_GCB_RST_SLEEP_US 100 #define VSC7512_GCB_RST_TIMEOUT_US 100000 @@ -96,6 +135,36 @@ static const struct resource vsc7512_sgpio_resources[] = { DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"), }; +const struct resource vsc7512_target_io_res[TARGET_MAX] = { + [ANA] = DEFINE_RES_REG_NAMED(VSC7512_ANA_RES_START, VSC7512_ANA_RES_SIZE, "ana"), + [QS] = DEFINE_RES_REG_NAMED(VSC7512_QS_RES_START, VSC7512_QS_RES_SIZE, "qs"), + [QSYS] = DEFINE_RES_REG_NAMED(VSC7512_QSYS_RES_START, VSC7512_QSYS_RES_SIZE, "qsys"), + [REW] = DEFINE_RES_REG_NAMED(VSC7512_REW_RES_START, VSC7512_REW_RES_SIZE, "rew"), + [SYS] = DEFINE_RES_REG_NAMED(VSC7512_SYS_RES_START, VSC7512_SYS_RES_SIZE, "sys"), + [S0] = DEFINE_RES_REG_NAMED(VSC7512_S0_RES_START, VSC7512_S_RES_SIZE, "s0"), + [S1] = DEFINE_RES_REG_NAMED(VSC7512_S1_RES_START, VSC7512_S_RES_SIZE, "s1"), + [S2] = DEFINE_RES_REG_NAMED(VSC7512_S2_RES_START, VSC7512_S_RES_SIZE, "s2"), + [GCB] = DEFINE_RES_REG_NAMED(VSC7512_GCB_RES_START, VSC7512_GCB_RES_SIZE, "devcpu_gcb"), + [HSIO] = DEFINE_RES_REG_NAMED(VSC7512_HSIO_RES_START, VSC7512_HSIO_RES_SIZE, "hsio"), +}; +EXPORT_SYMBOL_NS(vsc7512_target_io_res, MFD_OCELOT); + +const struct resource vsc7512_port_io_res[] = { + DEFINE_RES_REG_NAMED(VSC7512_PORT_0_RES_START, VSC7512_PORT_RES_SIZE, "port0"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_1_RES_START, VSC7512_PORT_RES_SIZE, "port1"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_2_RES_START, VSC7512_PORT_RES_SIZE, "port2"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_3_RES_START, VSC7512_PORT_RES_SIZE, "port3"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_4_RES_START, VSC7512_PORT_RES_SIZE, "port4"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_5_RES_START, VSC7512_PORT_RES_SIZE, "port5"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_6_RES_START, VSC7512_PORT_RES_SIZE, "port6"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_7_RES_START, VSC7512_PORT_RES_SIZE, "port7"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_8_RES_START, VSC7512_PORT_RES_SIZE, "port8"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_9_RES_START, VSC7512_PORT_RES_SIZE, "port9"), + DEFINE_RES_REG_NAMED(VSC7512_PORT_10_RES_START, VSC7512_PORT_RES_SIZE, "port10"), + {} +}; +EXPORT_SYMBOL_NS(vsc7512_port_io_res, MFD_OCELOT); + static const struct mfd_cell vsc7512_devs[] = { { .name = "ocelot-pinctrl", @@ -144,6 +213,7 @@ static void ocelot_core_try_add_regmaps(struct device *dev, int ocelot_core_init(struct device *dev) { + const struct resource *port_res; int i, ndevs; ndevs = ARRAY_SIZE(vsc7512_devs); @@ -151,6 +221,23 @@ int ocelot_core_init(struct device *dev) for (i = 0; i < ndevs; i++) ocelot_core_try_add_regmaps(dev, &vsc7512_devs[i]); + /* + * Both the target_io_res and the port_io_res structs need to be referenced directly by + * the ocelot_ext driver, so they can't be attached to the dev directly and referenced by + * offset like the rest of the drivers. Instead, create these regmaps always and allow any + * children look these up by name. + */ + for (i = 0; i < TARGET_MAX; i++) + /* + * The target_io_res array is sparsely populated. Use .start as an indication that + * the entry isn't defined + */ + if (vsc7512_target_io_res[i].start) + ocelot_core_try_add_regmap(dev, &vsc7512_target_io_res[i]); + + for (port_res = vsc7512_port_io_res; port_res->start; port_res++) + ocelot_core_try_add_regmap(dev, port_res); + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, vsc7512_devs, ndevs, NULL, 0, NULL); } EXPORT_SYMBOL_NS(ocelot_core_init, MFD_OCELOT); diff --git a/include/linux/mfd/ocelot.h b/include/linux/mfd/ocelot.h index dd72073d2d4f..439ff5256cf0 100644 --- a/include/linux/mfd/ocelot.h +++ b/include/linux/mfd/ocelot.h @@ -11,8 +11,13 @@ #include #include +#include + struct resource; +extern const struct resource vsc7512_target_io_res[TARGET_MAX]; +extern const struct resource vsc7512_port_io_res[]; + static inline struct regmap * ocelot_regmap_from_resource_optional(struct platform_device *pdev, unsigned int index,