From patchwork Wed Sep 14 21:15:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Li X-Patchwork-Id: 605922 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C837ECAAD3 for ; Wed, 14 Sep 2022 21:15:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229679AbiINVPt (ORCPT ); Wed, 14 Sep 2022 17:15:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229608AbiINVPs (ORCPT ); Wed, 14 Sep 2022 17:15:48 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE94A45F68; Wed, 14 Sep 2022 14:15:46 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6EFD4201AE1; Wed, 14 Sep 2022 23:15:45 +0200 (CEST) Received: from smtp.na-rdc02.nxp.com (usphx01srsp001v.us-phx01.nxp.com [134.27.49.11]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 024882004EB; Wed, 14 Sep 2022 23:15:45 +0200 (CEST) Received: from right.am.freescale.net (right.am.freescale.net [10.81.116.134]) by usphx01srsp001v.us-phx01.nxp.com (Postfix) with ESMTP id 6587F4060D; Wed, 14 Sep 2022 14:15:43 -0700 (MST) From: Li Yang To: shawnguo@kernel.org, devicetree@vger.kernel.org Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Priyanka Jain , Santan Kumar , Tao Yang , Yogesh Gaur , Abhimanyu Saini , Li Yang Subject: [PATCH v4 3/5] arm64: dts: ls2081a-rdb: Add DTS for NXP LS2081ARDB Date: Wed, 14 Sep 2022 16:15:36 -0500 Message-Id: <20220914211538.29473-4-leoyang.li@nxp.com> X-Mailer: git-send-email 2.25.1.377.g2d2118b In-Reply-To: <20220914211538.29473-1-leoyang.li@nxp.com> References: <20220914211538.29473-1-leoyang.li@nxp.com> MIME-Version: 1.0 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Priyanka Jain This patch adds support for NXP LS2081ARDB board which has LS2081A SoC. LS2081A SoC is 40-pin derivative of LS2088A SoC. From functional perspective both are same. Hence, LS2088a SoC dtsi file is included from LS2081ARDB dts. Signed-off-by: Priyanka Jain Signed-off-by: Santan Kumar Signed-off-by: Tao Yang Signed-off-by: Yogesh Gaur Signed-off-by: Abhimanyu Saini Signed-off-by: Li Yang --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/fsl-ls2081a-rdb.dts | 132 ++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 0815bc56fdbd..e712bbbf2257 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts new file mode 100644 index 000000000000..4461e16fd53a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for NXP LS2081A RDB Board. + * + * Copyright 2017 NXP + * + * Priyanka Jain + * + */ + +/dts-v1/; + +#include "fsl-ls2088a.dtsi" + +/ { + model = "NXP Layerscape 2081A RDB Board"; + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a"; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&dspi { + status = "okay"; + + n25q512a: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <3000000>; + reg = <0>; + }; +}; + +&esdhc { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + pca9547: mux@75 { + compatible = "nxp,pca9547"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <500>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + adt7481@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + }; +}; + +&ifc { + status = "disabled"; +}; + +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <20000000>; + reg = <0>; + }; + + s25fs512s1: flash@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + spi-max-frequency = <20000000>; + reg = <1>; + }; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +};