From patchwork Wed Sep 14 06:07:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 606800 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CDE1C6FA89 for ; Wed, 14 Sep 2022 06:08:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229926AbiINGIC (ORCPT ); Wed, 14 Sep 2022 02:08:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229758AbiINGIB (ORCPT ); Wed, 14 Sep 2022 02:08:01 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B142659DA; Tue, 13 Sep 2022 23:07:55 -0700 (PDT) X-UUID: c2642dec845648369cb5a8eda7b2a9ae-20220914 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=1OAmeDA6ar/po8UT6QCtGaslauKiW3mbQc6OuQ6RaAY=; b=noAtErndxSVSIHaIg27pDYUFGGSWV5cOcToFuraIULssJZWSkyj3UzozT9kYuMmEVHQKWkz4UBrKBEQyfyEOVSZVdw4nLXV5uR0AQTfBajwGD3xezWtj48UpvL8r1mUpcUcAmpaOBn5NyCzk0uiOOoPG80QWLnxZnZopEb0lEEE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:d2600dba-e369-49a8-b62f-544849d5eb08, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1, CLOUDID:72a656f6-6e85-48d9-afd8-0504bbfe04cb, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: c2642dec845648369cb5a8eda7b2a9ae-20220914 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 97364378; Wed, 14 Sep 2022 14:07:51 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 14 Sep 2022 14:07:50 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 14 Sep 2022 14:07:49 +0800 From: Chunfeng Yun To: Vinod Koul CC: Chunfeng Yun , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , , , , , , Eddie Hung , AngeloGioacchino Del Regno Subject: [PATCH v3 3/7] phy: phy-mtk-tphy: add property to set pre-emphasis Date: Wed, 14 Sep 2022 14:07:42 +0800 Message-ID: <20220914060746.10004-3-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914060746.10004-1-chunfeng.yun@mediatek.com> References: <20220914060746.10004-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a property to set usb2 phy's pre-emphasis, it's disabled by default on some SoCs. Signed-off-by: Chunfeng Yun --- v2~v3: no changes --- drivers/phy/mediatek/phy-mtk-tphy.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index 8ee7682b8e93..986fde0f63a0 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -72,6 +72,8 @@ #define PA5_RG_U2_HS_100U_U3_EN BIT(11) #define U3P_USBPHYACR6 0x018 +#define PA6_RG_U2_PRE_EMP GENMASK(31, 30) +#define PA6_RG_U2_PRE_EMP_VAL(x) ((0x3 & (x)) << 30) #define PA6_RG_U2_BC11_SW_EN BIT(23) #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) #define PA6_RG_U2_DISCTH GENMASK(7, 4) @@ -370,6 +372,7 @@ struct mtk_phy_instance { int eye_term; int intr; int discth; + int pre_emphasis; bool bc12_en; }; @@ -841,10 +844,13 @@ static void phy_parse_property(struct mtk_tphy *tphy, &instance->intr); device_property_read_u32(dev, "mediatek,discth", &instance->discth); + device_property_read_u32(dev, "mediatek,pre-emphasis", + &instance->pre_emphasis); dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n", instance->bc12_en, instance->eye_src, instance->eye_vrt, instance->eye_term, instance->intr, instance->discth); + dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis); } static void u2_phy_props_set(struct mtk_tphy *tphy, @@ -875,6 +881,10 @@ static void u2_phy_props_set(struct mtk_tphy *tphy, if (instance->discth) mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(instance->discth)); + + if (instance->pre_emphasis) + mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, + PA6_RG_U2_PRE_EMP_VAL(instance->pre_emphasis)); } /* type switch for usb3/pcie/sgmii/sata */