From patchwork Tue Sep 13 06:18:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 605485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52F89C54EE9 for ; Tue, 13 Sep 2022 06:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230256AbiIMGTI (ORCPT ); Tue, 13 Sep 2022 02:19:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230213AbiIMGSn (ORCPT ); Tue, 13 Sep 2022 02:18:43 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F14A57541 for ; Mon, 12 Sep 2022 23:18:42 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id i15-20020a17090a4b8f00b0020073b4ac27so10348096pjh.3 for ; Mon, 12 Sep 2022 23:18:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=5bvvWd4WtFmP4+rZD5AyV+ZxO3T7wivPuDP2w82MTho=; b=jApF67DKgFFG4O14T8MMLEVYllTFfzxVxqJv0QDe0Y7gZy5P4wy4+CYiVaDwLtddlL OR3wCdSbFRyImrrTVtWSMPC1kEFumV2I+PLI26CZ9+VZd3LMsPb4D+Mi3Byce+1hGzKH 0CEOu1pJP9J8A4z74Nllja0NAM/Vqqi1MX6yStEWz1yXQAEzCAzvowGS9ZT7tMjuhQNH Y0e1UnccGZtuBBvkj/KZFupslQYyZWFMZAaMTTfqidADyYnEhuItBVC97SLDTUrQW+r5 RZ/hSMoIWot9KCwGt+s6YkhhGyOS3ojPelCuGG9jcfiLHk97Oc6+DPknS4NUmMmijGhV eJgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=5bvvWd4WtFmP4+rZD5AyV+ZxO3T7wivPuDP2w82MTho=; b=UuKlK7LxiGO7BPPZ2NtHFRwUxVnt5V0/Pb6PhYuRAfU3g5OiakxIal5SmzeRSbg6ft lbJUDSqXjiy2HKz3v3SLCsHVPWYHeUpysivlEQefyhL5guZdBEkMwXn2g15sGiDtspW4 CNPo4/bcJG9isk+FkD+T56k+k+Tgj+Kpn2LD1lOnne6R0CBADktBNMgcB/As8/+0QpPP STbpnP0MeCB1WzjqHqKACO0yO2njWh3Ze1Fg1DTFQ3pwzsgeEN3ua2JW5Lc4m37WDoaD ZAMuL5wMCgm86PmsTYEsWyxiXo0Quvjsh+a9RGQh0Fl+SMkRjkY0hXAKvjHTgR8SJl6Y du8w== X-Gm-Message-State: ACgBeo05iCSazMeTch+yB9RwzY+XTHngDcKBs4nzsQUMZly3zwPHBKeS g8h5kU/PT+D7+OZZvCCuU4CB8Q== X-Google-Smtp-Source: AA6agR7ohooCghBf34n40h3VqSzgxuUDH9DmUDn6UjYI5sZtusgmGig7dwtb1cLx7HzbGSjvzgji/A== X-Received: by 2002:a17:90a:e293:b0:202:6eab:acac with SMTP id d19-20020a17090ae29300b002026eabacacmr2229554pjz.203.1663049922048; Mon, 12 Sep 2022 23:18:42 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id z11-20020a170902cccb00b00173cfaed233sm7296332ple.62.2022.09.12.23.18.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 23:18:41 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v5 6/7] soc: sifive: ccache: define the macro for the register shifts Date: Tue, 13 Sep 2022 06:18:16 +0000 Message-Id: <20220913061817.22564-7-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220913061817.22564-1-zong.li@sifive.com> References: <20220913061817.22564-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li Reviewed-by: Conor Dooley --- drivers/soc/sifive/sifive_ccache.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 91f0c2b32ea2..1c171150e878 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -33,6 +34,11 @@ #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 #define SIFIVE_CCACHE_CONFIG 0x00 +#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0) +#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8) +#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) +#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) + #define SIFIVE_CCACHE_WAYENABLE 0x08 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 @@ -87,11 +93,11 @@ static void ccache_config_read(void) u32 cfg; cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - - pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", - (cfg & 0xff), (cfg >> 8) & 0xff, - BIT_ULL((cfg >> 16) & 0xff), - BIT_ULL((cfg >> 24) & 0xff)); + pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n", + FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg), + FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg), + BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)), + BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg))); cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); pr_info("Index of the largest way enabled: %u\n", cfg);