diff mbox series

[v3,03/15] hwspinlock: qcom: correct MMIO max register for newer SoCs

Message ID 20220909092035.223915-4-krzysztof.kozlowski@linaro.org
State Accepted
Commit 90cb380f9ceb811059340d06ff5fd0c0e93ecbe1
Headers show
Series [v3,01/15] dt-bindings: hwlock: qcom-hwspinlock: add support for MMIO on older SoCs | expand

Commit Message

Krzysztof Kozlowski Sept. 9, 2022, 9:20 a.m. UTC 
Newer ARMv8 Qualcomm SoCs using 0x1000 register stride have maximum
register 0x20000 (32 mutexes * 0x1000).

Fixes: 7a1e6fb1c606 ("hwspinlock: qcom: Allow mmio usage in addition to syscon")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
 drivers/hwspinlock/qcom_hwspinlock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c
index 80ea45b3a815..9734e149d981 100644
--- a/drivers/hwspinlock/qcom_hwspinlock.c
+++ b/drivers/hwspinlock/qcom_hwspinlock.c
@@ -121,7 +121,7 @@  static const struct regmap_config tcsr_mutex_config = {
 	.reg_bits		= 32,
 	.reg_stride		= 4,
 	.val_bits		= 32,
-	.max_register		= 0x40000,
+	.max_register		= 0x20000,
 	.fast_io		= true,
 };