From patchwork Thu Sep 8 22:28:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 603936 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31341C6FA82 for ; Thu, 8 Sep 2022 22:29:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229895AbiIHW25 (ORCPT ); Thu, 8 Sep 2022 18:28:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229977AbiIHW24 (ORCPT ); Thu, 8 Sep 2022 18:28:56 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3F7AF3437 for ; Thu, 8 Sep 2022 15:28:54 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id z20so21688707ljq.3 for ; Thu, 08 Sep 2022 15:28:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=En/eL17w8Q/uCNcnjjzqqx4odQyBNyedY5XKGx95FUo=; b=hz5GskQjLm/GyiSHYzLGdBHtf9q/KGB1xe75sD0SldaMqac3bjn4CEzPHSQYYyCPBy IpnG8ccapIfrox4VAT7xgoXSjNbB+oNeC6X53MlZMB6ppZF2RbDt9jQvmeHmjFYhpOUs MQsrJX7ff8u2ZUeunc27kgq+vr0633F5WTtppeIv+dJS9ROQSbXY8cSXOWuZAV8Inr4n QIU45ltLWFh8pG++yWAXx3pD7vN9DUOaDsQDAghL2OFJ9RthA6zDAbJMz1aKOES0mao3 Jn7oVHeb6tqFJ3BpbnCejkpqLLrfp6o4JGDrNSPkHI7Thn0AIbMQyYPErC99M+5FsaIV vFzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=En/eL17w8Q/uCNcnjjzqqx4odQyBNyedY5XKGx95FUo=; b=VdzImrgKuy6tNQmUi82axJQzBG7OeQ0o+LVKU96K2UyWDWecyDfO9s2Q5O7eH7p6J4 vVs9o/yBQ1NGWnt1yG+WeoXz9ezm0e0xKdQZn8wQ6N1uxGzOLNYTdLtdOabvVaSIUrGP vIi7n79uxAyNLCXmuO7bjtqpU2n5249aqcD3lVnu/gIA6VzwEFhTvns6LamYjKyXakfn 4CBBw/nutTa0ffhdbgmalcOzWSCzv3oYYjMjSDR44tzVWpZMX7kuaTlYW59SivdYmtLa ifkEpBCEadJhfIOwTX4Hvs3WV2avvDI2K2nAwzIYAKKyXYxu1m4tYs8xeEvrwxTrGzdb dTRg== X-Gm-Message-State: ACgBeo3naFxdW0Ck70Ol79SRqo687PL0LWPBAwYcggRVfZjQ4y7YUloz hYxPWoZOmnn9zs6/AXxYzosbms0jmAt+NQ== X-Google-Smtp-Source: AA6agR4Xwz3yqrA/X+LCyqYtb1p9nxG29mcnXMqt0O5YTfFG7HQGCcpz64+w6sjIWQ8RQIm1AFei6g== X-Received: by 2002:a2e:1f01:0:b0:25f:ea3a:4ef0 with SMTP id f1-20020a2e1f01000000b0025fea3a4ef0mr2982511ljf.330.1662676132877; Thu, 08 Sep 2022 15:28:52 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id a25-20020ac25e79000000b00497a3e11608sm1389078lfr.303.2022.09.08.15.28.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 15:28:52 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 2/4] clk: qcom: alpha-pll: add support for power off mode for lucid evo PLL Date: Fri, 9 Sep 2022 01:28:48 +0300 Message-Id: <20220908222850.3552050-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220908222850.3552050-1-dmitry.baryshkov@linaro.org> References: <20220908222850.3552050-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PLLs can be kept in standby (default configuration) or in off mode when disabled during power collapse. Hence add support for pll disable off mode for lucid evo PLL. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-alpha-pll.c | 40 +++++++++++++++++++++++++++++--- drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index b42684703fbb..9cc38234d45d 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2088,7 +2088,7 @@ static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) return ret; } -static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) +static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); struct regmap *regmap = pll->clkr.regmap; @@ -2117,9 +2117,12 @@ static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) /* Place the PLL mode in STANDBY */ regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY); + + if (reset) + regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0); } -static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) +static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset) { struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); struct clk_hw *p; @@ -2139,11 +2142,31 @@ static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) if (ret) return ret; - alpha_pll_lucid_evo_disable(hw); + _alpha_pll_lucid_evo_disable(hw, reset); return 0; } +static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) +{ + _alpha_pll_lucid_evo_disable(hw, false); +} + +static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw) +{ + return _alpha_pll_lucid_evo_prepare(hw, false); +} + +static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw) +{ + _alpha_pll_lucid_evo_disable(hw, true); +} + +static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw) +{ + return _alpha_pll_lucid_evo_prepare(hw, true); +} + static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -2191,6 +2214,17 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = { }; EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops); +const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = { + .prepare = alpha_pll_reset_lucid_evo_prepare, + .enable = alpha_pll_lucid_evo_enable, + .disable = alpha_pll_reset_lucid_evo_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = alpha_pll_lucid_evo_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = alpha_pll_lucid_5lpe_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops); + void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config) { diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 447efb82fe59..ea90a61bf774 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -155,6 +155,7 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops; #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops extern const struct clk_ops clk_alpha_pll_lucid_evo_ops; +extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops; extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;