From patchwork Thu Sep 8 18:35:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerry Ray X-Patchwork-Id: 603950 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D09BC54EE9 for ; Thu, 8 Sep 2022 18:36:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232090AbiIHSgS (ORCPT ); Thu, 8 Sep 2022 14:36:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232144AbiIHSfw (ORCPT ); Thu, 8 Sep 2022 14:35:52 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76EDDE902F; Thu, 8 Sep 2022 11:35:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662662151; x=1694198151; h=from:to:subject:date:message-id:in-reply-to:references: mime-version; bh=p245WdqkxMiC917qGj7IdsEfOZL8PguJjlKzlA+i/dM=; b=HIXwuo9hJFz138plNVB3KYVVowCR+FWrP7JXTnFsle+48cRDVeNtNgLl kBKgS2hhTZw8iFNNffwsTMoG09JKh7WlTHcrf0Ec7XItD02TrpJsRrDWv ITJBGKiWCJfLV1HWHykx946UpwrOIatIQhyz936vAFnVTaMkndHHjH26N hXuUERbZrB8xt63ZOXXQGhHCWJ4i02Wg4RPVhfnmRaSTFYV8g0ebFqAZ1 e8cX8sdWFoG3Ktirf6UDDMYAUgUtH9/XErpTBQiHF++FjVqXvZa+Lu81P rjzHCyEliujX7Fk60/IQ/QGzXbYz2mDkqA9ZXLCWBzZnKwuvCY7FlYClG Q==; X-IronPort-AV: E=Sophos;i="5.93,300,1654585200"; d="scan'208";a="173015061" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Sep 2022 11:35:49 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 8 Sep 2022 11:35:39 -0700 Received: from AUS-LT-C33025.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 8 Sep 2022 11:35:38 -0700 From: Jerry Ray To: Krzysztof Kozlowski , Rob Herring , Nicolas Ferre , "Alexandre Belloni" , Claudiu Beznea , , , , "Jerry Ray" Subject: [linux][PATCH v7 2/2] ARM: dts: at91: Add SAMA5D3-EDS Board Date: Thu, 8 Sep 2022 13:35:37 -0500 Message-ID: <20220908183537.8004-2-jerry.ray@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220908183537.8004-1-jerry.ray@microchip.com> References: <20220908183537.8004-1-jerry.ray@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SAMA5D3-EDS board is an Ethernet Development Platform allowing for evaluating many Microchip ethernet switch and PHY products. Various daughter cards can connect via an RGMII connector or an RMII connector. The EDS board is not intended for stand-alone use and has no ethernet capabilities when no daughter board is connected. As such, this device tree is intended to be used with a DT overlay defining the add-on board. To better ensure consistency, some items are defined here as a form of documentation so that all add-on overlays will use the same terms. Link: https://www.microchip.com/en-us/development-tool/SAMA5D3-ETHERNET-DEVELOPMENT-SYSTEM Signed-off-by: Jerry Ray --- v6->v7: - Renamed regulators, making things more consistent. - Made slow_xtal and main_xtal entries direct overrides. v5->v6: - Replaced underscores in names where I can, improving naming. v4->v5: - patch now applies to v6.0-rc2 v3->v4: - Fixed regulators as necessary to get the board to boot from SD Card. v2->v3: - Alphabetized pinctrl entries. - cleaned up a warning in the regulators section. - License tweaked to 'OR MIT' - Included Makefile change v1->v2: - Modified the compatible field in the device tree to reflect Microchip Ethernet Development System Board. --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/at91-sama5d3_eds.dts | 307 +++++++++++++++++++++++++ 2 files changed, 308 insertions(+) create mode 100644 arch/arm/boot/dts/at91-sama5d3_eds.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 05d8aef6e5d2..e92e639a2dc3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -61,6 +61,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d2_icp.dtb \ at91-sama5d2_ptc_ek.dtb \ at91-sama5d2_xplained.dtb \ + at91-sama5d3_eds.dtb \ at91-sama5d3_ksz9477_evb.dtb \ at91-sama5d3_xplained.dtb \ at91-dvk_som60.dtb \ diff --git a/arch/arm/boot/dts/at91-sama5d3_eds.dts b/arch/arm/boot/dts/at91-sama5d3_eds.dts new file mode 100644 index 000000000000..c7fbf7aa7826 --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d3_eds.dts @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet + * Development System board. + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Jerry Ray + */ +/dts-v1/; +#include "sama5d36.dtsi" + +/ { + model = "SAMA5D3 Ethernet Development System"; + compatible = "microchip,sama5d3-eds", "atmel,sama5d36", + "atmel,sama5d3", "atmel,sama5"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + button-3 { + label = "PB_USER"; + gpios = <&pioE 29 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + memory@20000000 { + reg = <0x20000000 0x10000000>; + }; + + vcc_3v3_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_2v5_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "VCC_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + vin-supply = <&vcc_3v3_reg>; + }; + + vcc_1v8_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vcc_3v3_reg>; + }; + + vcc_1v2_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_mmc0_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "mmc0-card-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>; + gpio = <&pioE 2 GPIO_ACTIVE_LOW>; + }; +}; + +&can0 { + status = "okay"; +}; + +&dbgu { + status = "okay"; +}; + +&ebi { + pinctrl-0 = <&pinctrl_ebi_nand_addr>; + pinctrl-names = "default"; + status = "okay"; + + nand_controller: nand-controller { + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x2>; + atmel,rb = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0xc0000>; + }; + + bootloaderenvred@100000 { + label = "bootloader env redundant"; + reg = <0x100000 0x40000>; + }; + + bootloaderenv@140000 { + label = "bootloader env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + }; +}; + +&i2c0 { + pinctrl-0 = <&pinctrl_i2c0_pu>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&pinctrl_i2c2_pu>; + status = "okay"; +}; + +&main_xtal { + clock-frequency = <12000000>; +}; + +&mmc0 { + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 + &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>; + vmmc-supply = <&vcc_mmc0_reg>; + vqmmc-supply = <&vcc_3v3_reg>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <8>; + cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + board { + pinctrl_i2c0_pu: i2c0-pu { + atmel,pins = + , + ; + }; + + pinctrl_i2c2_pu: i2c2-pu { + atmel,pins = + , + ; + }; + + pinctrl_key_gpio: key-gpio-0 { + atmel,pins = + ; + }; + + pinctrl_mmc0_cd: mmc0-cd { + atmel,pins = + ; + }; + + /* Reserved for reset signal to the RGMII connector. */ + pinctrl_rgmii_rstn: rgmii-rstn { + atmel,pins = + ; + }; + + /* Reserved for an interrupt line from the RMII and RGMII connectors. */ + pinctrl_spi_irqn: spi-irqn { + atmel,pins = + ; + }; + + pinctrl_spi0_cs: spi0-cs-default { + atmel,pins = + ; + }; + + pinctrl_spi1_cs: spi1-cs-default { + atmel,pins = ; + }; + + pinctrl_usba_vbus: usba-vbus { + atmel,pins = + ; + }; + + pinctrl_usb_default: usb-default { + atmel,pins = + ; + }; + + /* Reserved for VBUS fault interrupt. */ + pinctrl_vbusfault_irqn: vbusfault-irqn { + atmel,pins = + ; + }; + + pinctrl_vcc_mmc0_reg_gpio: vcc-mmc0-reg-gpio-default { + atmel,pins = ; + }; + }; +}; + +&slow_xtal { + clock-frequency = <32768>; +}; + +&spi0 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi0_cs>; + cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default", "cs"; + pinctrl-1 = <&pinctrl_spi1_cs>; + cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioC 28 0>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&usb0 { /* USB Device port with VBUS detection. */ + atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { /* 3-port Host. First port is unused. */ + atmel,vbus-gpio = <0 + &pioE 3 GPIO_ACTIVE_HIGH + &pioE 4 GPIO_ACTIVE_HIGH + >; + num-ports = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +};