| Message ID | 20220908111712.665287-9-conor.dooley@microchip.com |
|---|---|
| State | Accepted |
| Commit | fa52935abef422d119dda3c10c02787a86e6289d |
| Headers | show |
| Series | New PolarFire SoC devkit devicetrees & 22.09 reference design updates | expand |
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 98f04be0dc6b..c2aac1a7e862 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -30,7 +30,7 @@ i2c2: i2c@40000200 { fabric_clk3: fabric-clk3 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <62500000>; + clock-frequency = <50000000>; }; fabric_clk1: fabric-clk1 {
For the v2022.09 release of the reference design, the fic3 clock rate been reduced from 62.5 MHz to 50 MHz as it allows timing to be closed significantly more quickly by customers who chose to build the reference design themselves. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)