From patchwork Wed Aug 31 18:58:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 601539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC9DBC3DA6B for ; Wed, 31 Aug 2022 18:59:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232965AbiHaS7r (ORCPT ); Wed, 31 Aug 2022 14:59:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233060AbiHaS7i (ORCPT ); Wed, 31 Aug 2022 14:59:38 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56DFEC2761 for ; Wed, 31 Aug 2022 11:58:42 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id w19so12617203ljj.7 for ; Wed, 31 Aug 2022 11:58:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=bv3T8WPYFThl+f9nEQNBZ4CF4xXVMlb0Mv8v7lUGZ9g=; b=aeavUBuAflc0zIZCHvHEfsXPKQhTBnWi6Sod5ZpwlETq/fMQ0AuF8SWBFA7kVpMpKF xyLhscZfyprTnovwf7238DdIx3PFFgnQGMhxlvkzKWqEr7eqcfoZIiqpk5bduEyiZnOn r671SIwnWuRVluTfdrNXV8fgRbG86JPwkWQnY1qdBvv1pBuUbwEi8OimwPSbg2pLrLwD aCY2OEmby0pyBCuE195HoHHAmSovEs28nh0mPIg97mIwMiqWS+WpY6JplVd2gSWxQ06E tpQ1DEYHaUmO8FEyE/UVYsJapAWPX2iIjcJjGZ/NXw/BJbOHNcovcMggdDVfDY2bWpxK kAEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=bv3T8WPYFThl+f9nEQNBZ4CF4xXVMlb0Mv8v7lUGZ9g=; b=poAdrN90lrk8hC2OtYa73jsK4sAOyDXRSP/R1jt8Ll3rbpNmxq0Cpf4MqYEgeRT/Qn abWeWrDhHuQ65CDxnJvlSM8ChoVxSRdKX5bLci5i3g71s4u1JycusjEaIxylLFHlO4sP GEPg3rPE1k2TFWb6Wn4jIAsvEJJqo144Kha5pEdk31T1FuJQry+AQoNYcJzcAZjdyL65 jqrnhWN5IOCTWFCq6p1nEmT5G4l3YXgVAIqTRa6EXKtShqT9PFn9MLzhyG9N//nZG72O ZP4HOlWn64bNti8G7Nlxkn10m5uAWOWstr+oLKtAANupXt48ICFWteGfHJr7I5Fs1rpP JpqA== X-Gm-Message-State: ACgBeo2nl4AmLhZkGg8XiA9SQmdN6O+4upfW6p3d3X6i+S50jyEd8iJq JAEQGJSl0d5BjsxeWy3VwOHjNw== X-Google-Smtp-Source: AA6agR6gxKnik2KrBf/SiNFCpBy9rGaiP0wIH21aVrg45VkskAR9SPI1ShF4BLwBEd9XjnRb7AHfpw== X-Received: by 2002:a2e:844a:0:b0:255:46b9:5e86 with SMTP id u10-20020a2e844a000000b0025546b95e86mr8258434ljh.388.1661972321795; Wed, 31 Aug 2022 11:58:41 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g1-20020a0565123b8100b004948f583e6bsm322422lfv.138.2022.08.31.11.58.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Aug 2022 11:58:41 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno , Loic Poulain Subject: [PATCH v5 12/12] dt-bindings: display/msm: add support for the display on SM8250 Date: Wed, 31 Aug 2022 21:58:30 +0300 Message-Id: <20220831185830.1798676-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220831185830.1798676-1-dmitry.baryshkov@linaro.org> References: <20220831185830.1798676-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM8250 platform. Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/dpu-sm8250.yaml | 96 ++++++++++++++++ .../bindings/display/msm/mdss-common.yaml | 4 +- .../bindings/display/msm/mdss-sm8250.yaml | 106 ++++++++++++++++++ 3 files changed, 204 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml create mode 100644 Documentation/devicetree/bindings/display/msm/mdss-sm8250.yaml diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml new file mode 100644 index 000000000000..9bc2ee4a6589 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-sm8250.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SM8250 + +maintainers: + - Dmitry Baryshkov + +description: | + Device tree bindings for the DPU display controller for SM8250 target. + +allOf: + - $ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8250-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display ahb clock + - description: Display hf axi clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-controller@ae01000 { + compatible = "qcom,sm8250-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "iface", "bus", "core", "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8250_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index 053c1e889552..a0a54cd63100 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -27,11 +27,11 @@ properties: clocks: minItems: 2 - maxItems: 3 + maxItems: 4 clock-names: minItems: 2 - maxItems: 3 + maxItems: 4 interrupts: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/msm/mdss-sm8250.yaml b/Documentation/devicetree/bindings/display/msm/mdss-sm8250.yaml new file mode 100644 index 000000000000..d581d10fea2d --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/mdss-sm8250.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/mdss-sm8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display MDSS dt properties for SM8250 target + +maintainers: + - Krishna Manikandan + +description: | + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SM8250 target. + +allOf: + - $ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm8250-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8250-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,mdss-dsi-ctrl + + "^dsi-phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-7nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sm8250-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x820 0x402>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; +...