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PTR:InfoNoRecords; CAT:NONE; SFS:(13230016)(4636009)(39860400002)(346002)(376002)(136003)(396003)(36840700001)(46966006)(40470700004)(70206006)(6666004)(70586007)(107886003)(2906002)(41300700001)(7696005)(8676002)(8936002)(40460700003)(336012)(4326008)(2616005)(40480700001)(36860700001)(186003)(83380400001)(426003)(478600001)(47076005)(5660300002)(86362001)(1076003)(81166007)(356005)(26005)(82310400005)(82740400003)(36756003)(110136005)(316002)(54906003)(36900700001)(16060500005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2022 11:44:39.3008 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86ec5f4c-06ef-4eba-a779-08da89b3db17 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT048.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3649 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra234 has eight single-channel PWM controllers, one of them in the AON block. Signed-off-by: Sandipan Patra --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 81a0f599685f..c2dc651f0842 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -840,6 +840,90 @@ #pwm-cells = <2>; }; + pwm2: pwm@3290000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x3290000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM2>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM2>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm3: pwm@32a0000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x32a0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM3>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM3>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm4: pwm@c340000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0xc340000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM4>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM4>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm5: pwm@32c0000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x32c0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM5>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM5>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm6: pwm@32d0000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x32d0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM6>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM6>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm7: pwm@32e0000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x32e0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM7>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM7>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + + pwm8: pwm@32f0000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x32f0000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM8>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM8>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + spi@3300000 { compatible = "nvidia,tegra234-qspi"; reg = <0x3300000 0x1000>;