From patchwork Mon Aug 22 15:51:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 599345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3FC9C32774 for ; Mon, 22 Aug 2022 15:52:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236817AbiHVPwM (ORCPT ); Mon, 22 Aug 2022 11:52:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236783AbiHVPwL (ORCPT ); Mon, 22 Aug 2022 11:52:11 -0400 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2083.outbound.protection.outlook.com [40.107.22.83]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 607532AC7E; Mon, 22 Aug 2022 08:52:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Qltts+PccpoGwOviBgy59bIl1Va8FPutBNY1d+mhSThA5H0Sv64RWvUvIgjCIYmgZMk6KBwbd3xQvIcMJHNgu4Tcb/QU1C+6ViHYZKduyAgM2BsDaZirrcqIVDtIErMmCSIWnn6LNInm6numsF9ziW6frEKRnw/DpfK+7w9IVud4zr3bPE5hzpaB/sjyBlGm+E3zYVs75a/Y+FiyOZx/ZYM2N+O7p2mqjikoMJeZWNGijp/3fqWBdck8cqW7wKOit+2/XGnL5g1cl1auQC0LJVgUDIi6vVSJLY8OZH+BkXq/ezw+4ZKECUli4S0LoqMygf0E33kGMsdPxZkGmZHVLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0FTN6H7ukeDkJqVfwyfo0imFQDw/M5zvxApyhzWREEs=; b=OvCI2Oeq9MPi1D35E1NBsY4LO4A2/uOSpGZ6qxvgf0pLn33Bbc4r12MnIFUna8N/gQm8DlBPS+MaNu5y53v/TKC2b7HaFnl3dKtViKGGDC3C2dZYTuYeShldU7N3AC1gfeAIcGmJpHEw/m3t1J0FJ35uUfJB7wyPATv+0JbNKrnVofNw+rW+A2xtUEOoPXkQlDYL0xiWzKL7aA+yc8mqNoF2zIPLEfHTjCS9BndKo7jOB+St0MFHbasA0uxiIF1v9RK54S3VD7pycAtfOTISa5vg7J84I/d6aLYaMkbBbn9Ux1pONCbWIGDzrw0XZ/1584DgB4xY5wuWkIcj5PXaNQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0FTN6H7ukeDkJqVfwyfo0imFQDw/M5zvxApyhzWREEs=; b=eLa9SErOB3Z7qwCX7u5YR3BjX3AXPcjBGxD7FOuf8CkQYNfZVX8mqVVTtOfFzmCCuFgM+oZQzaNvXr7iEv+NeKjqAtdXqjLtxtsFnKhleG2X6wIBBzs09l6Q35fTml/hePHGG0KjkToU6b3Q5PZzVpkOVzzay1P2dm9iL+/txXA= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9186.eurprd04.prod.outlook.com (2603:10a6:102:232::18) by AM5PR04MB3169.eurprd04.prod.outlook.com (2603:10a6:206:4::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5546.22; Mon, 22 Aug 2022 15:52:01 +0000 Received: from PAXPR04MB9186.eurprd04.prod.outlook.com ([fe80::85cb:614b:9f52:2dba]) by PAXPR04MB9186.eurprd04.prod.outlook.com ([fe80::85cb:614b:9f52:2dba%4]) with mapi id 15.20.5546.022; Mon, 22 Aug 2022 15:52:01 +0000 From: Frank Li To: maz@kernel.org, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kw@linux.com, bhelgaas@google.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, jdmason@kudzu.us, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com, ntb@lists.linux.dev, lznuaa@gmail.com Subject: [PATCH v7 2/4] irqchip: Add IMX MU MSI controller driver Date: Mon, 22 Aug 2022 10:51:28 -0500 Message-Id: <20220822155130.2491006-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220822155130.2491006-1-Frank.Li@nxp.com> References: <20220822155130.2491006-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR13CA0038.namprd13.prod.outlook.com (2603:10b6:a03:2c2::13) To PAXPR04MB9186.eurprd04.prod.outlook.com (2603:10a6:102:232::18) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 652281de-8a9e-4be9-509d-08da84564075 X-MS-TrafficTypeDiagnostic: AM5PR04MB3169:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2Kw5cnsc0yHkVaW3pr/WlL12URMh9FJGPqYeJNvWWCzPcxdgWDthVxJv6eqJ1fRmJEwB6KJd1o/HmB+Lxz74N91MwKByS/Io0tJVAU0DC0GKELaSutx2NAkLmQjBTxh4MDWN4eLdaH4hhJE4tgM34/BW3Dqse1fudeb7MUpayPaoMv9GXcEEi1zzk8QP1X/8wDgnKVETpr2D6Bq7jzlVNn2Mia+RNOu3+39DBD1EPLaMAqA3U0B3F9/BSXX8qnSnvw4aeFCvs3TmaPCXkxW2MgpDhYuoX/PV2kuK6M7Qq4QTohoanY2NMrEblWR33bKnV5yJCXlAjeDzlZqFkL6zXItf4J3J5gFPacwD9mulwQqZMm+0Psy1sR4BbHSm1KOiPzjQuvun4diXNijaycr9fBuDlhs0ZHcY7hIoE9mJdIUuNfbd0xusgSghCCvfWyy8bEXdsLKSRVPfqJ9InBjlMw7khxsz3OpanH4Sxyyv58+7on/UooyGykZNFpJwbFUghDg2l/dXGYSdMuweaDX+QwC2gfp9mAfHsowRqO9hgA4MuIWnatHE4P0EBuB3uB0p1yULM+uHSzMq1B4tSoC0vp7dUf/ee7RHiC7Um/xdskDwQhIcWewe8OYzYrkSNht4ODZH4Q1heTNMo/YS6L0c3QLxgZpHDfFrJicB6LtUEGoCm4Vd/1lxzFkolxANYwBLBGxLYhBMHWiPGbJMPSq7f9X3+l7us2Kg5KDVxJLd+a42M8Ver2GEX4SSJ/X2iBKRqTo2fpibQMVRyKpf6Kswhg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PAXPR04MB9186.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(4636009)(346002)(39860400002)(366004)(136003)(396003)(376002)(316002)(86362001)(38100700002)(38350700002)(36756003)(41300700001)(83380400001)(26005)(6506007)(52116002)(6666004)(6486002)(6512007)(478600001)(2906002)(66946007)(66556008)(66476007)(1076003)(8936002)(30864003)(5660300002)(8676002)(7416002)(2616005)(4326008)(186003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /2mAS4MX1m+NnFWooW+Pq2hX8F2kNVqbSIbMe8BCwp/+HZ+IyGC66Gd+/fHfs07TXBQIAhyvnWqJStfGVvtLp0gqeUpat6OI3TFVu0QxXCJNxlhosrXC4qm2oH3QWvQU5+k7ZRjN0tQEWfavIeQJg5+0Ezd5acFY+EmY5sWbQekmdDEQFDo8mEpJO29HxLYjLO4S7ved1ZinkV5TGwpwLs1yWolwyxfTNI763sQBmdSK/tAt33WyoKrx7TN2jByzWPwFa9xDhIW8pIIAxWIHQsDkCzMDEdMWF82OYJK6TD7HgAnRTrxTFSTMzC+d7W5FYge5pPqq5JwTNMRk+XdUM4KFLxZbQ137jHnJuoXlIAm73ykqWvWjw/y+/v1KPXfXZeeRFm7aJiJKASEMCiZbP3EeUt72/poqSxQXrM66QYQCcHLATvCiR3gKmiOlr9IIOqguF0iLCaDYZ2TNuBiFRQo2dLHpvXzvlIgz2lnwKTJLZgJi9RVz9nd5TtbYQ9aKCt39f/BorTV77YcrybzKrjZsEZlLKgbzJuDE9wxpjuTUPRnJXTfzsb0rGhQTdZRiN28m5kgk4vka1R2Vv5B3ua4L0GMiVDRVwCY5UL7ylyIT0SSRASCv/AfEP7xo2EPGedHFv8ZNyv9IeaYm42cWnyK4D/SvQg/50b8VIHIn1WUSs2cZHq3+WQx2Ys02V7qILdjnRVOXtkICej5H71El5m2PayXd3UW1tOMUCWjaDJ1I16uei+Woo4gxZTXONoAwATM/n75AyxYyPYJ2FBlY7xazaeXwdlevdzIAu5IT0w5sehN1wUqE5r19homWkQaRbBLbyTW9oWysj6T60a9GrOyICBxQBQRC0zrH0Xx5OCJFXxL0igI1o6MixPoJgx5YhrIgaed71no1mAtvXTw7ui62C27f2ggS9SeYFnBTyjUQGUmtUkyMNSodMvngzf7NEbI2JGNlRNJMJazh1CvjaCLZEw+MFTEACCFRT40q6EX9xAXOFHCysn3h5xjzs2PLHRSd337nqc5U9H3Ynb1cSqa/KMwpCm9YUaBQDmNUbyUwL4wV0BepTJAt+acY1IV00Oml9hoVWpB18zOoWwllioB6Q9XTSjoJ9bn55Xd0qR0lw2OzYN+Y+PfXg8X65B5rp5AqigmjoKyQt0b/vZOy8MVimWnF3km7kkQSJp1qh+/YmMvYbln0Lupm6oB1nldyY/O1doqNA0NDAK9uaPG/sQ16Da0Zmy38QJxUSuDN2lkLbHxI96Y3aLGrzxMoe6gwcTcrJyenlV8/RFOP3SHv2EmmWfQmreTjcwT/QSNTURPy0u3vh8nsWFAVBNK7+/Sxbf3VgRM58x0+PtwwX8bN8R6Eqd/hPEEg9dx+XuZY9uTSaGjEAg8EIWVqSlR0O1JISrVZFbA5GJnHTTPYnRg187O5dYvhBtaxmcCrDorqt6IpLIay4gb/3T5fBY90yVqhBU+WC7PPD0Ud4oCo8pUWdllf6GV6N6MbtJ8Ecs6hKymeUseShFbpT7pzraRTw23gmgUipdwyO0hu899LEHOWb6o0jUboJo1skd6goLN9jS+4e26wvSccaJa36UspEUi6 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 652281de-8a9e-4be9-509d-08da84564075 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9186.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 15:52:01.2950 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: at8ntAKp9LJAzyrux148EdlTLT3iXzDTviZCNhjeM3fnlAZJe0R8CfohSLCNVhZ/+XCpDo0ZSj/65mgJsecQPQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR04MB3169 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The MU block found in a number of Freescale/NXP SoCs supports generating IRQs by writing data to a register This enables the MU block to be used as a MSI controller, by leveraging the platform-MSI API Signed-off-by: Frank Li --- drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-imx-mu-msi.c | 451 +++++++++++++++++++++++++++++++ 3 files changed, 461 insertions(+) create mode 100644 drivers/irqchip/irq-imx-mu-msi.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 5e4e50122777d..e04c6521dce55 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -470,6 +470,15 @@ config IMX_INTMUX help Support for the i.MX INTMUX interrupt multiplexer. +config IMX_MU_MSI + bool "i.MX MU work as MSI controller" + default y if ARCH_MXC + select IRQ_DOMAIN + select IRQ_DOMAIN_HIERARCHY + select GENERIC_MSI_IRQ_DOMAIN + help + MU work as MSI controller to do general doorbell + config LS1X_IRQ bool "Loongson-1 Interrupt Controller" depends on MACH_LOONGSON32 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 5d8e21d3dc6d8..870423746c783 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -98,6 +98,7 @@ obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o obj-$(CONFIG_IMX_INTMUX) += irq-imx-intmux.o +obj-$(CONFIG_IMX_MU_MSI) += irq-imx-mu-msi.o obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o diff --git a/drivers/irqchip/irq-imx-mu-msi.c b/drivers/irqchip/irq-imx-mu-msi.c new file mode 100644 index 0000000000000..110e5df1d6aa8 --- /dev/null +++ b/drivers/irqchip/irq-imx-mu-msi.c @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Freescale MU worked as MSI controller + * + * Copyright (c) 2018 Pengutronix, Oleksij Rempel + * Copyright 2022 NXP + * Frank Li + * Peng Fan + * + * Based on drivers/mailbox/imx-mailbox.c + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define IMX_MU_CHANS 4 + +enum imx_mu_xcr { + IMX_MU_GIER, + IMX_MU_GCR, + IMX_MU_TCR, + IMX_MU_RCR, + IMX_MU_xCR_MAX, +}; + +enum imx_mu_xsr { + IMX_MU_SR, + IMX_MU_GSR, + IMX_MU_TSR, + IMX_MU_RSR, +}; + +enum imx_mu_type { + IMX_MU_V1 = BIT(0), + IMX_MU_V2 = BIT(1), + IMX_MU_V2_S4 = BIT(15), +}; + +/* Receive Interrupt Enable */ +#define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) +#define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) + +struct imx_mu_dcfg { + enum imx_mu_type type; + u32 xTR; /* Transmit Register0 */ + u32 xRR; /* Receive Register0 */ + u32 xSR[4]; /* Status Registers */ + u32 xCR[4]; /* Control Registers */ +}; + +struct imx_mu_msi { + spinlock_t lock; + raw_spinlock_t reglock; + struct irq_domain *msi_domain; + void __iomem *regs; + phys_addr_t msiir_addr; + const struct imx_mu_dcfg *cfg; + unsigned long used; + struct clk *clk; +}; + +static void imx_mu_write(struct imx_mu_msi *msi_data, u32 val, u32 offs) +{ + iowrite32(val, msi_data->regs + offs); +} + +static u32 imx_mu_read(struct imx_mu_msi *msi_data, u32 offs) +{ + return ioread32(msi_data->regs + offs); +} + +static u32 imx_mu_xcr_rmw(struct imx_mu_msi *msi_data, enum imx_mu_xcr type, u32 set, u32 clr) +{ + unsigned long flags; + u32 val; + + raw_spin_lock_irqsave(&msi_data->reglock, flags); + val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); + val &= ~clr; + val |= set; + imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); + raw_spin_unlock_irqrestore(&msi_data->reglock, flags); + + return val; +} + +static void imx_mu_msi_parent_mask_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); + + imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data, data->hwirq)); +} + +static void imx_mu_msi_parent_unmask_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); + + imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data, data->hwirq), 0); +} + +static void imx_mu_msi_parent_ack_irq(struct irq_data *data) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); + + imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4); +} + +static struct irq_chip imx_mu_msi_irq_chip = { + .name = "MU-MSI", + .irq_ack = irq_chip_ack_parent, +}; + +static struct msi_domain_ops imx_mu_msi_irq_ops = { +}; + +static struct msi_domain_info imx_mu_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .ops = &imx_mu_msi_irq_ops, + .chip = &imx_mu_msi_irq_chip, +}; + +static void imx_mu_msi_parent_compose_msg(struct irq_data *data, + struct msi_msg *msg) +{ + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); + u64 addr = msi_data->msiir_addr + 4 * data->hwirq; + + msg->address_hi = upper_32_bits(addr); + msg->address_lo = lower_32_bits(addr); + msg->data = data->hwirq; +} + +static int imx_mu_msi_parent_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static struct irq_chip imx_mu_msi_parent_chip = { + .name = "MU", + .irq_mask = imx_mu_msi_parent_mask_irq, + .irq_unmask = imx_mu_msi_parent_unmask_irq, + .irq_ack = imx_mu_msi_parent_ack_irq, + .irq_compose_msi_msg = imx_mu_msi_parent_compose_msg, + .irq_set_affinity = imx_mu_msi_parent_set_affinity, +}; + +static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, + void *args) +{ + struct imx_mu_msi *msi_data = domain->host_data; + unsigned long flags; + int pos, err = 0; + + WARN_ON(nr_irqs != 1); + + spin_lock_irqsave(&msi_data->lock, flags); + pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS); + if (pos < IMX_MU_CHANS) + __set_bit(pos, &msi_data->used); + else + err = -ENOSPC; + spin_unlock_irqrestore(&msi_data->lock, flags); + + if (err) + return err; + + irq_domain_set_info(domain, virq, pos, + &imx_mu_msi_parent_chip, msi_data, + handle_edge_irq, NULL, NULL); + return 0; +} + +static void imx_mu_msi_domain_irq_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(d); + unsigned long flags; + + spin_lock_irqsave(&msi_data->lock, flags); + __clear_bit(d->hwirq, &msi_data->used); + spin_unlock_irqrestore(&msi_data->lock, flags); +} + +static const struct irq_domain_ops imx_mu_msi_domain_ops = { + .alloc = imx_mu_msi_domain_irq_alloc, + .free = imx_mu_msi_domain_irq_free, +}; + +static void imx_mu_msi_irq_handler(struct irq_desc *desc) +{ + struct imx_mu_msi *msi_data = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + u32 status; + int i; + + status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]); + + chained_irq_enter(chip, desc); + for (i = 0; i < IMX_MU_CHANS; i++) { + if (status & IMX_MU_xSR_RFn(msi_data, i)) + generic_handle_domain_irq(msi_data->msi_domain, i); + } + chained_irq_exit(chip, desc); +} + +static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data, struct device *dev) +{ + struct fwnode_handle *fwnodes = dev_fwnode(dev); + struct irq_domain *parent; + + /* Initialize MSI domain parent */ + parent = irq_domain_create_linear(fwnodes, + IMX_MU_CHANS, + &imx_mu_msi_domain_ops, + msi_data); + if (!parent) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } + + irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); + + msi_data->msi_domain = platform_msi_create_irq_domain( + fwnodes, + &imx_mu_msi_domain_info, + parent); + + if (!msi_data->msi_domain) { + dev_err(dev, "failed to create MSI domain\n"); + irq_domain_remove(parent); + return -ENOMEM; + } + + irq_domain_set_pm_device(msi_data->msi_domain, dev); + + return 0; +} + +/* Register offset of different version MU IP */ +static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { + .xTR = 0x0, + .xRR = 0x10, + .xSR = {0x20, 0x20, 0x20, 0x20}, + .xCR = {0x24, 0x24, 0x24, 0x24}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { + .xTR = 0x20, + .xRR = 0x40, + .xSR = {0x60, 0x60, 0x60, 0x60}, + .xCR = {0x64, 0x64, 0x64, 0x64}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { + .type = IMX_MU_V2, + .xTR = 0x200, + .xRR = 0x280, + .xSR = {0xC, 0x118, 0x124, 0x12C}, + .xCR = {0x110, 0x114, 0x120, 0x128}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { + + .type = IMX_MU_V2 | IMX_MU_V2_S4, + .xTR = 0x200, + .xRR = 0x280, + .xSR = {0xC, 0x118, 0x124, 0x12C}, + .xCR = {0x110, 0x114, 0x120, 0x128}, +}; + +static int __init imx_mu_of_init(struct device_node *dn, + struct device_node *parent, + const struct imx_mu_dcfg *cfg + ) +{ + struct platform_device *pdev = of_find_device_by_node(dn); + struct device_link *pd_link_a; + struct device_link *pd_link_b; + struct imx_mu_msi *msi_data; + struct resource *res; + struct device *pd_a; + struct device *pd_b; + struct device *dev; + int ret; + int irq; + + if (!pdev) + return -ENODEV; + + dev = &pdev->dev; + + msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); + if (!msi_data) + return -ENOMEM; + + msi_data->cfg = cfg; + + msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "processor a-facing"); + if (IS_ERR(msi_data->regs)) { + dev_err(&pdev->dev, "failed to initialize 'regs'\n"); + return PTR_ERR(msi_data->regs); + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor b-facing"); + if (!res) + return -EIO; + + msi_data->msiir_addr = res->start + msi_data->cfg->xTR; + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) + return -ENODEV; + + platform_set_drvdata(pdev, msi_data); + + msi_data->clk = devm_clk_get(dev, NULL); + if (IS_ERR(msi_data->clk)) { + if (PTR_ERR(msi_data->clk) != -ENOENT) + return PTR_ERR(msi_data->clk); + + msi_data->clk = NULL; + } + + pd_a = dev_pm_domain_attach_by_name(dev, "processor a-facing"); + if (IS_ERR(pd_a)) + return PTR_ERR(pd_a); + + pd_b = dev_pm_domain_attach_by_name(dev, "processor b-facing"); + if (IS_ERR(pd_b)) + return PTR_ERR(pd_b); + + pd_link_a = device_link_add(dev, pd_a, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + + if (!pd_link_a) { + dev_err(dev, "Failed to add device_link to mu a.\n"); + goto err_pd_a; + } + + pd_link_b = device_link_add(dev, pd_b, + DL_FLAG_STATELESS | + DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + + + if (!pd_link_b) { + dev_err(dev, "Failed to add device_link to mu a.\n"); + goto err_pd_b; + } + + ret = imx_mu_msi_domains_init(msi_data, dev); + if (ret) + goto err_dm_init; + + irq_set_chained_handler_and_data(irq, + imx_mu_msi_irq_handler, + msi_data); + + pm_runtime_enable(dev); + + return 0; + +err_dm_init: + device_link_remove(dev, pd_b); +err_pd_b: + device_link_remove(dev, pd_a); +err_pd_a: + return -EINVAL; +} + +static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) +{ + struct imx_mu_msi *priv = dev_get_drvdata(dev); + + clk_disable_unprepare(priv->clk); + + return 0; +} + +static int __maybe_unused imx_mu_runtime_resume(struct device *dev) +{ + struct imx_mu_msi *priv = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(priv->clk); + if (ret) + dev_err(dev, "failed to enable clock\n"); + + return ret; +} + +static const struct dev_pm_ops imx_mu_pm_ops = { + SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, + imx_mu_runtime_resume, NULL) +}; + +static int __init imx_mu_imx7ulp_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx7ulp); +} + +static int __init imx_mu_imx6sx_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx6sx); +} + +static int __init imx_mu_imx8ulp_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp); +} + +static int __init imx_mu_imx8ulp_s4_of_init(struct device_node *dn, + struct device_node *parent) +{ + return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp_s4); +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(imx_mu_msi) +IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init) +IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init) +IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init) +IRQCHIP_MATCH("fsl,imx8ulp-mu-msi-s4", imx_mu_imx8ulp_s4_of_init) +IRQCHIP_PLATFORM_DRIVER_END(imx_mu_msi, .pm = &imx_mu_pm_ops) + + +MODULE_AUTHOR("Frank Li "); +MODULE_DESCRIPTION("Freescale MU MSI controller driver"); +MODULE_LICENSE("GPL");