From patchwork Fri Aug 5 12:18:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jerome Neanne X-Patchwork-Id: 595618 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 605C0C25B08 for ; Fri, 5 Aug 2022 12:19:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240716AbiHEMTM (ORCPT ); Fri, 5 Aug 2022 08:19:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237996AbiHEMTI (ORCPT ); Fri, 5 Aug 2022 08:19:08 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F180578220 for ; Fri, 5 Aug 2022 05:19:06 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id e13so3109395edj.12 for ; Fri, 05 Aug 2022 05:19:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc; bh=unDWnF6HPmVWReddvgna+5d9gjeuo0raSvPQa0BEduo=; b=L2Iw0f6QqFnxvHpQZx1RKYQRMJIcN2uSxqz2ZFl1nMmvB5wRe7FhqOwWh4SrABpWx1 twFImOeI4yxodTkB/FR4sw6CP3SF/G69ha39oIeIdhzYkEyaf264aeRVckc8bHaZMERB 0EQaHo5zwSI7RKSG/K+UFJFBAhHNG6zlPCeILj85q3TbTonCMNzfpnwFXsBSBrPi+Fnt 8oJw68tBYSRtaYSdtDIUmcniMavAtFJql/xamLg9+gvFphlY90emFf8VjdExWshct95j kHWai7ihKf+bAKdbQGgadmoqV03DylXfROrVPxZXXAVJuQ1AuhiPxS/PcVlSh+b1H3TI woaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc; bh=unDWnF6HPmVWReddvgna+5d9gjeuo0raSvPQa0BEduo=; b=thXWJ/vPY6L94HJWekEBe/1Y7V79JotrshM/2AMXSh66kmv8lZPlMG2AKwYwk+DiY5 MWnoW/vTTUT/DfJltj+Ycv0P/XmJDk587UrOi6/QjadYwskFt8dp8t9xRY73G/KY9vPP oOvqp+qrZIvdNHy+koJz8gyx4FoCG48B4D9dt1W4crrJ1FoMApplPkUX1RbYuIeMmFD8 FpNrsP6iFgASkBwhIjatLgZurafzynsJesbzUIHO9vOIWR+AvETk2afsLvWVcvTHqLPA A3Vv7hhmZ3NSUxyRlBJjT5DF5vtnxgwdBZG03mUm3rIBN0xnjePt86CBz4I0Vzx8DTzi geaA== X-Gm-Message-State: ACgBeo0WM9d6c5aEVfsha/kAo6D+/BIDOtNC2fzMLUfLKXCvVmWfIe4z 5ECG0j+12swL/eNYRcszXzNc4g== X-Google-Smtp-Source: AA6agR6I8Ts90gv0xcLO6i3FVR8tZU2PU9eEjeiG437F7M3n5uMeDxVxWBhahrKXMGwxebZcUC120g== X-Received: by 2002:a05:6402:292:b0:43c:ee5e:a5da with SMTP id l18-20020a056402029200b0043cee5ea5damr6428365edv.181.1659701945406; Fri, 05 Aug 2022 05:19:05 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-5241-be09-b892-f882-607f-7a79.rev.sfr.net. [2a02:8440:5241:be09:b892:f882:607f:7a79]) by smtp.gmail.com with ESMTPSA id kx13-20020a170907774d00b0072b3464c043sm1506111ejc.116.2022.08.05.05.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Aug 2022 05:19:04 -0700 (PDT) From: Jerome Neanne To: lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org, nm@ti.com, kristo@kernel.org, dmitry.torokhov@gmail.com Cc: khilman@baylibre.com, narmstrong@baylibre.com, msp@baylibre.com, j-keerthy@ti.com, lee.jones@linaro.org, jneanne@baylibre.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 01/10] DONOTMERGE: arm64: dts: ti: Add TI TPS65219 PMIC support for AM642 SK board. Date: Fri, 5 Aug 2022 14:18:43 +0200 Message-Id: <20220805121852.21254-2-jneanne@baylibre.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220805121852.21254-1-jneanne@baylibre.com> References: <20220805121852.21254-1-jneanne@baylibre.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support fot the TI Power Management IC TPS65219 on the AM642 SKEVM board. Needed for driver testing but official board support pending. TI commitment is required before board upstream kick-off. Signed-off-by: Jerome Neanne --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 104 +++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 2620469a7517..565b50810579 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -150,6 +150,20 @@ vin-supply = <&com8_ls_en>; gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; }; + + vsel_sd_nddr: gpio-regulator { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel_sd_nddr_pins_default>; + regulator-name = "tps65219-LDO1-SEL-SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&ldo1_reg>; + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; }; &main_pmx0 { @@ -181,6 +195,13 @@ >; }; + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -267,6 +288,12 @@ AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ >; }; + + vsel_sd_nddr_pins_default: vsel-sd-nddr-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 7) /* (Y7) PRG1_PRU0_GPO0.GPIO0_45 */ + >; + }; }; &mcu_uart0 { @@ -315,6 +342,83 @@ status = "disabled"; }; +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + tps65219: pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + system-power-controller; + + buck1-supply = <&vcc_3v3_sys>; + buck2-supply = <&vcc_3v3_sys>; + buck3-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&buck2_reg>; + ldo3-supply = <&vcc_3v3_sys>; + ldo4-supply = <&vcc_3v3_sys>; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "VCC1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_LPDDR4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "VDDSHV_SD_IO_PMIC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + }; + + ldo2_reg: ldo2 { + regulator-name = "VDDAR_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "VDD_PHY_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; &main_i2c1 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>;