From patchwork Sun Jul 31 17:47:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 594675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F641C19F2B for ; Sun, 31 Jul 2022 17:48:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237248AbiGaRsP (ORCPT ); Sun, 31 Jul 2022 13:48:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232336AbiGaRsO (ORCPT ); Sun, 31 Jul 2022 13:48:14 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC280E0D3 for ; Sun, 31 Jul 2022 10:48:13 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id v16-20020a17090abb9000b001f25244c65dso12944318pjr.2 for ; Sun, 31 Jul 2022 10:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=vofowt60zIc/lnFVlyI4BeBG85w8rxNk/k1iZ0Ct+8A=; b=ar8l0q9L46UWX+F9Te/v4KS9Qv+yBtO9qlnaSB7xA56F6wxLpdimuSzgf+Yd4agg6u wLLhi/OI2E4eoB5bZez0owlgCLZ1PYl9A+/JQ3Pm7MCrcR1yhCB5N6fqcBaizCykahkV yeyvccrWse5G1tIIESVKF1uGfIvQ1d+RxcSfGb4D1nhkHuQ5f5UJ2EmESIr+Zznefr6w 3YKRUD7t1iN8DJa8de3JLj/gZH45AB2pC1fH3gVLQ+ksBgMdfCMbW+6fOqdt4jeC6gOu j2Af2OauFURpdlr8/MiTxSRKgQZ1GA1EGbr++tp+hCVdmH1+zdAVBTGnxiL2NgGyVber Ykww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=vofowt60zIc/lnFVlyI4BeBG85w8rxNk/k1iZ0Ct+8A=; b=LP9XwpllIC43aNU9V/PY8fMUqxo36RCLNGpeDHbBUcVJMDEhS6HWIR5TEVyZYJEuJT 6sDBOfy8xGHZ2bREVxLJxo95M2b/B6FCDxQ62XEuYv63vbPTBjug8efuDmOgIO7hrzmm rLFZXhC+bVGOZZAaceXM0eavQXK21GplbGmVRAFVx/LEcqzj7Dk7+4VPVdXQxDwKv6N0 MMN+J71AbjQ+H1EQP1XOBJLouwq/impLwcmibx5LUGJDjXIw/SHSzGViTxntPFzjyXqm VomfqX9mScc7gcgUMo92hbLisv11y5plLyl3tZ5faqcfBk44bw7YFUsw9FMcv6cCYxtb QQOw== X-Gm-Message-State: ACgBeo3yoi6/IbGfLxyh71lGJKV5/vA3pePS5/nO8Ui09kW+Jn/bKRzC kcMDLftCPTpCjy9rhD/Yg/Sctw== X-Google-Smtp-Source: AA6agR4d276bFmsiyju9FRb8KWzEgmWCJbVK/qluicSptnCXw2Eq+I1YDnJA5AFgCC5tAqrvE7lLDQ== X-Received: by 2002:a17:90a:6b45:b0:1e3:3cfa:3104 with SMTP id x5-20020a17090a6b4500b001e33cfa3104mr15915990pjl.113.1659289693383; Sun, 31 Jul 2022 10:48:13 -0700 (PDT) Received: from localhost.localdomain ([2405:201:c00a:a073:c5e8:48d3:6a8c:6418]) by smtp.gmail.com with ESMTPSA id n5-20020a170903110500b0016d3935eff0sm7812062plh.176.2022.07.31.10.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jul 2022 10:48:13 -0700 (PDT) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Kever Yang Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Jagan Teki , linux-clk@vger.kernel.org, Michael Turquette , Stephen Boyd , Krzysztof Kozlowski Subject: [PATCH v2 09/20] dt-bindings: clock: rockchip: Document RV1126 CRU Date: Sun, 31 Jul 2022 23:17:15 +0530 Message-Id: <20220731174726.72631-10-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220731174726.72631-1-jagan@edgeble.ai> References: <20220731174726.72631-1-jagan@edgeble.ai> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document dt-bindings for Rockchip RV1126 clock controller. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette Cc: Stephen Boyd Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jagan Teki --- Changes for v2: - fixed title - remove '|' in description - add one example .../bindings/clock/rockchip,rv1126-cru.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml new file mode 100644 index 000000000000..0998f8b922bd --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RV1126 Clock and Reset Unit + +maintainers: + - Jagan Teki + - Finley Xiao + - Heiko Stuebner + +description: + The RV1126 clock controller generates the clock and also implements a + reset controller for SoC peripherals. + +properties: + compatible: + enum: + - rockchip,rv1126-cru + - rockchip,rv1126-pmucru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + };