From patchwork Tue Jul 26 18:06:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar Mahadev Lad X-Patchwork-Id: 593580 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F04AAC04A68 for ; Tue, 26 Jul 2022 18:06:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233676AbiGZSG5 (ORCPT ); Tue, 26 Jul 2022 14:06:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234575AbiGZSGw (ORCPT ); Tue, 26 Jul 2022 14:06:52 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7DD952A726; Tue, 26 Jul 2022 11:06:50 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,194,1654527600"; d="scan'208";a="129202689" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 27 Jul 2022 03:06:49 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9CB0740C58A7; Wed, 27 Jul 2022 03:06:45 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Anup Patel , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list Date: Tue, 26 Jul 2022 19:06:20 +0100 Message-Id: <20220726180623.1668-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220726180623.1668-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. In preparation to add support for RZ/Five SoC add the Andes AX45MP core to the list. More details about Andes AX45MP core can be found here: [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ Signed-off-by: Lad Prabhakar --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index ffa8f12c29af..e941b2821d23 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -27,6 +27,7 @@ properties: oneOf: - items: - enum: + - andestech,ax45mp - canaan,k210 - sifive,bullet0 - sifive,e5