From patchwork Tue Jul 26 02:35:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chukun Pan X-Patchwork-Id: 593906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 358A3C43334 for ; Tue, 26 Jul 2022 02:35:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231313AbiGZCfc (ORCPT ); Mon, 25 Jul 2022 22:35:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230489AbiGZCfc (ORCPT ); Mon, 25 Jul 2022 22:35:32 -0400 X-Greylist: delayed 230 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 25 Jul 2022 19:35:31 PDT Received: from mail-m121145.qiye.163.com (mail-m121145.qiye.163.com [115.236.121.145]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B32665F4; Mon, 25 Jul 2022 19:35:31 -0700 (PDT) Received: from amadeus-VLT-WX0.lan (unknown [113.118.189.34]) by mail-m121145.qiye.163.com (Hmail) with ESMTPA id AE788800091; Tue, 26 Jul 2022 10:35:28 +0800 (CST) From: Chukun Pan To: Heiko Stuebner Cc: Michael Riesch , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Chukun Pan Subject: [PATCH] arm64: dts: rockchip: Enable PCIe controller on rock3a Date: Tue, 26 Jul 2022 10:35:16 +0800 Message-Id: <20220726023516.6487-1-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUtXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVkZTRoaVh1OHUgdQkMfTU4fTFUTARMWGhIXJBQOD1 lXWRgSC1lBWUpKSFVKSkNVSkNCVUhPWVdZFhoPEhUdFFlBWU9LSFVKSktISkNVS1kG X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Pj46SCo5Gj0#PE4WN05DMAsC KBAKCzVVSlVKTU5DQ0tJQklCT05KVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUpK SFVKSkNVSkNCVUhPWVdZCAFZQUhLQkw3Bg++ X-HM-Tid: 0a82385bfd6eb03akuuuae788800091 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the nodes to enable the PCIe controller on the Radxa ROCK3 Model A board. Run test with the MT7921 pcie wireless card. Signed-off-by: Chukun Pan --- .../boot/dts/rockchip/rk3568-rock-3a.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 0813c0c5abde..3ce7eb05defc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -119,6 +119,18 @@ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { regulator-max-microvolt = <5000000>; vin-supply = <&vcc5v0_usb>; }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_enable_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; }; &combphy0 { @@ -129,6 +141,10 @@ &combphy1 { status = "okay"; }; +&combphy2 { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; @@ -423,6 +439,14 @@ rgmii_phy1: ethernet-phy@0 { }; }; +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_h>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + &pinctrl { ethernet { eth_phy_rst: eth_phy_rst { @@ -436,6 +460,16 @@ led_user_en: led_user_en { }; }; + pcie { + pcie_enable_h: pcie-enable-h { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_reset_h: pcie-reset-h { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic_int { rockchip,pins =