From patchwork Sun Jul 24 18:23:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 593206 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A36BBC43334 for ; Sun, 24 Jul 2022 18:24:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231217AbiGXSYC (ORCPT ); Sun, 24 Jul 2022 14:24:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230373AbiGXSYC (ORCPT ); Sun, 24 Jul 2022 14:24:02 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9073B7EC; Sun, 24 Jul 2022 11:24:00 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id ez10so16691799ejc.13; Sun, 24 Jul 2022 11:24:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+bKtCBqbS+CKrPUHr+7B/BEcgmKfUspeyLuIWD2yzlY=; b=knZF72y6QtChyf0wBkInXUuHz1Y/VR0/ELwKcNjoBJDPwadA0tS0jJKWlTii2VDdkP 5JLFs3ubdOHK5KdXyhFazf2uj4DYN7fQneWcN8cG/SuCPuJ5RmYOmsoN8FuJmbazKwsm NUPgVP7Ghz3Xlt3iVN8ixazDv/qlmN2fK0oaZ7jfx/ULxhPWQOFjqVeHW4HCB1k6yfBF r9zJT/B8P47gp8dww7vMDcnvFRqlex0+Aukd8t0zHVMxGsJ/IcJhcusLEmL2nTnTOASR +BHa0cHPG5fzFQSDeDBWU6smYn7WldVT6Sf+LZMJF3z3+OMWABtMeTA9lXCq2p0mrHDX MvoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+bKtCBqbS+CKrPUHr+7B/BEcgmKfUspeyLuIWD2yzlY=; b=gP5wI71BaTYqpRcdqlPkacn/WvSyAUy+yR1IVXNKVKPLFDR7nWGLik3+B8YNPAo6lQ ptEKgNIn0CxOwAgcFvZQ8xDfdTpoNhJE2D99oGzC7o8B+BlwX5IAP1NYLidXU3N6NWgL 6TxXLirNh+5TG6irakVc0iG2f77D9B0DTRDDrh62uaqirzY0dhfqrh0xbCWAeqAvrxo7 9fkfMR862uH/vnExYsq6/Dk2WOOG0g07Ux8rY3R/zbDajc+FvkX52hlGOIMtpmB05Z/V YsjhCuv0LUIhFZQMDskarhBTVlctSvBr/+dSbOMoqpjoiif52wu3bLZV7M9IXFygnQrA QL0A== X-Gm-Message-State: AJIora/NtAsFVLO1SKClDhV8VBRwMhaKG2dUaWKXTijODJMrbaMzb+4C 0XyfB+ArGW1v+HbUlGlcHEA= X-Google-Smtp-Source: AGRyM1unLgFH7CDEHS1CLWiTcEviE/67ObhBt+a4rCaf0NbAUiGl/XQuM+UGuv8cqDPN2F7rlKm4/Q== X-Received: by 2002:a17:906:5a5b:b0:72b:39cf:6042 with SMTP id my27-20020a1709065a5b00b0072b39cf6042mr7102720ejc.301.1658687039342; Sun, 24 Jul 2022 11:23:59 -0700 (PDT) Received: from localhost.localdomain ([5.171.121.144]) by smtp.googlemail.com with ESMTPSA id kw24-20020a170907771800b0072b609d9a36sm502680ejc.16.2022.07.24.11.23.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Jul 2022 11:23:58 -0700 (PDT) From: Christian Marangi To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Christian Marangi , Dmitry Baryshkov Subject: [PATCH v7 3/4] clk: qcom: lcc-ipq806x: convert to parent data Date: Sun, 24 Jul 2022 20:23:28 +0200 Message-Id: <20220724182329.9891-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220724182329.9891-1-ansuelsmth@gmail.com> References: <20220724182329.9891-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert lcc-ipq806x driver to parent_data API. Change parent_name for pll4 to pxo_board to prepare the future to eventually drop the double pxo board clk. Signed-off-by: Christian Marangi Reviewed-by: Dmitry Baryshkov --- v7: - Add info about changed pxo clk - Add review tag v6: - Split to separate patch for ARRAY_SIZE - Rename .name to pxo_board - Drop _clk from .fw_name v5: - Fix the same compilation error (don't know what the hell happen to my buildroot) v4: - Fix compilation error v3: - Inline pxo pll4 parent - Change .name from pxo to pxo_board drivers/clk/qcom/lcc-ipq806x.c | 69 +++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 31 deletions(-) diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c index ba90bebba597..1833e59a6434 100644 --- a/drivers/clk/qcom/lcc-ipq806x.c +++ b/drivers/clk/qcom/lcc-ipq806x.c @@ -34,7 +34,9 @@ static struct clk_pll pll4 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll4", - .parent_names = (const char *[]){ "pxo" }, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "pxo", .name = "pxo_board", + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_pll4_map[] = { { P_PLL4, 2 } }; -static const char * const lcc_pxo_pll4[] = { - "pxo", - "pll4_vote", +static const struct clk_parent_data lcc_pxo_pll4[] = { + { .fw_name = "pxo", .name = "pxo_board" }, + { .fw_name = "pll4_vote", .name = "pll4_vote" }, }; static struct freq_tbl clk_tbl_aif_mi2s[] = { @@ -131,7 +133,7 @@ static struct clk_rcg mi2s_osr_src = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "mi2s_osr_src", - .parent_names = lcc_pxo_pll4, + .parent_data = lcc_pxo_pll4, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -139,10 +141,6 @@ static struct clk_rcg mi2s_osr_src = { }, }; -static const char * const lcc_mi2s_parents[] = { - "mi2s_osr_src", -}; - static struct clk_branch mi2s_osr_clk = { .halt_reg = 0x50, .halt_bit = 1, @@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk = { .enable_mask = BIT(17), .hw.init = &(struct clk_init_data){ .name = "mi2s_osr_clk", - .parent_names = lcc_mi2s_parents, + .parent_hws = (const struct clk_hw*[]) { + &mi2s_osr_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_clk = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "mi2s_div_clk", - .parent_names = lcc_mi2s_parents, + .parent_hws = (const struct clk_hw*[]) { + &mi2s_osr_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_regmap_div_ops, }, @@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_clk = { .enable_mask = BIT(15), .hw.init = &(struct clk_init_data){ .name = "mi2s_bit_div_clk", - .parent_names = (const char *[]){ "mi2s_div_clk" }, + .parent_hws = (const struct clk_hw*[]) { + &mi2s_div_clk.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_clk = { }, }; +static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = { + { .hw = &mi2s_bit_div_clk.clkr.hw, }, + { .fw_name = "mi2s_codec", .name = "mi2s_codec_clk" }, +}; static struct clk_regmap_mux mi2s_bit_clk = { .reg = 0x48, @@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_clk = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "mi2s_bit_clk", - .parent_names = (const char *[]){ - "mi2s_bit_div_clk", - "mi2s_codec_clk", - }, - .num_parents = 2, + .parent_data = lcc_mi2s_bit_div_codec_clk, + .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -245,7 +250,7 @@ static struct clk_rcg pcm_src = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "pcm_src", - .parent_names = lcc_pxo_pll4, + .parent_data = lcc_pxo_pll4, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pcm_clk_out", - .parent_names = (const char *[]){ "pcm_src" }, + .parent_hws = (const struct clk_hw*[]) { + &pcm_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = { }, }; +static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = { + { .hw = &pcm_clk_out.clkr.hw, }, + { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" }, +}; + static struct clk_regmap_mux pcm_clk = { .reg = 0x54, .shift = 10, @@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "pcm_clk", - .parent_names = (const char *[]){ - "pcm_clk_out", - "pcm_codec_clk", - }, - .num_parents = 2, + .parent_data = lcc_pcm_clk_out_codec_clk, + .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -325,7 +334,7 @@ static struct clk_rcg spdif_src = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "spdif_src", - .parent_names = lcc_pxo_pll4, + .parent_data = lcc_pxo_pll4, .num_parents = 2, .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -333,10 +342,6 @@ static struct clk_rcg spdif_src = { }, }; -static const char * const lcc_spdif_parents[] = { - "spdif_src", -}; - static struct clk_branch spdif_clk = { .halt_reg = 0xd4, .halt_bit = 1, @@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = { .enable_mask = BIT(12), .hw.init = &(struct clk_init_data){ .name = "spdif_clk", - .parent_names = lcc_spdif_parents, + .parent_hws = (const struct clk_hw*[]) { + &spdif_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -384,7 +391,7 @@ static struct clk_rcg ahbix_clk = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "ahbix", - .parent_names = lcc_pxo_pll4, + .parent_data = lcc_pxo_pll4, .num_parents = 2, .ops = &clk_rcg_lcc_ops, },