From patchwork Wed Jul 20 12:30:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 591942 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBA5FCCA480 for ; Wed, 20 Jul 2022 12:30:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239036AbiGTMat (ORCPT ); Wed, 20 Jul 2022 08:30:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236846AbiGTMah (ORCPT ); Wed, 20 Jul 2022 08:30:37 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFDE7481EB; Wed, 20 Jul 2022 05:30:35 -0700 (PDT) X-UUID: a3dfb7056c3a449d8e3c3a1a02299133-20220720 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:514aee7d-9715-4ba0-85c5-d362b6366dc1, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:0f94e32, CLOUDID:b8547d33-b9e4-42b8-b28a-6364427c76bb, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: a3dfb7056c3a449d8e3c3a1a02299133-20220720 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 997632278; Wed, 20 Jul 2022 20:30:27 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 20 Jul 2022 20:30:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 20 Jul 2022 20:30:25 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Lee Jones , Matthias Brugger , Tinghan Shen , AngeloGioacchino Del Regno , MandyJH Liu CC: , , , , , , YT Lee Subject: [PATCH v3 11/21] arm64: dts: mt8195: Add cpufreq node Date: Wed, 20 Jul 2022 20:30:13 +0800 Message-ID: <20220720123023.13500-12-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220720123023.13500-1-tinghan.shen@mediatek.com> References: <20220720123023.13500-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: YT Lee Add cpufreq node for mt8195. Signed-off-by: YT Lee Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 8032b839dfe8..900aaa16f862 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -26,6 +26,7 @@ compatible = "arm,cortex-a55"; reg = <0x000>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; @@ -38,6 +39,7 @@ compatible = "arm,cortex-a55"; reg = <0x100>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; @@ -50,6 +52,7 @@ compatible = "arm,cortex-a55"; reg = <0x200>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; @@ -62,6 +65,7 @@ compatible = "arm,cortex-a55"; reg = <0x300>; enable-method = "psci"; + performance-domains = <&performance 0>; clock-frequency = <1701000000>; capacity-dmips-mhz = <578>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; @@ -74,6 +78,7 @@ compatible = "arm,cortex-a78"; reg = <0x400>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; @@ -86,6 +91,7 @@ compatible = "arm,cortex-a78"; reg = <0x500>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; @@ -98,6 +104,7 @@ compatible = "arm,cortex-a78"; reg = <0x600>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; @@ -110,6 +117,7 @@ compatible = "arm,cortex-a78"; reg = <0x700>; enable-method = "psci"; + performance-domains = <&performance 1>; clock-frequency = <2171000000>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpu_off_b &cluster_off_b>; @@ -231,6 +239,12 @@ clock-output-names = "clk32k"; }; + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupt-parent = <&gic>;