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Miller" , Jakub Kicinski , Madalin Bucur , netdev@vger.kernel.org Cc: Paolo Abeni , Eric Dumazet , linux-arm-kernel@lists.infradead.org, Russell King , linux-kernel@vger.kernel.org, Sean Anderson , Krzysztof Kozlowski , Li Yang , Rob Herring , Shawn Guo , devicetree@vger.kernel.org Subject: [PATCH net-next v3 44/47] arm64: dts: ls1046a: Add serdes bindings Date: Fri, 15 Jul 2022 17:59:51 -0400 Message-Id: <20220715215954.1449214-45-sean.anderson@seco.com> X-Mailer: git-send-email 2.35.1.1320.gc452695387.dirty In-Reply-To: <20220715215954.1449214-1-sean.anderson@seco.com> References: <20220715215954.1449214-1-sean.anderson@seco.com> X-ClientProxiedBy: CH2PR10CA0009.namprd10.prod.outlook.com (2603:10b6:610:4c::19) To VI1PR03MB4973.eurprd03.prod.outlook.com (2603:10a6:803:c5::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1a80fd86-61d7-4ebd-e632-08da66ada12c X-MS-TrafficTypeDiagnostic: HE1PR03MB2857:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NgMZ1cO8szdcaopUGgrR/M7AjUQORhsmPvidRblEHDS0pu1YP18qH6J9HTKjQE8SgnbCItKOqec4MOAdV/7nkLBnwwx7XQfcFqlB9cfM4tfHwENPY7ESWe3YroTmLsUpyb9CkXgaG+GsgmM6CPqqKUdQMaS00ZltXXc2RKf4EGYl22RVEO9xUNEsDjCw1FD6AoKyM1CKqizYEGSbeBj6hwUm+sFTxNJ9A7c+QkUj4AX/OE5wv5ARbLDGrIGYkPQUq3OsElPZIaEo3smmYONjirC+TjF2LIKZ8UOdffY1vXd2KFJqMAB8rzFNA+dMdrkPjFDHL0H84el8JKmrcaFr1MT7qepqJadw3J6J+JRt3y8TetcvfJhkc3ZryMWuWR3FTney4oqdnD9A/Xu0Wil+TqbbQ+gQ0ZKNQZHhfkTr2PVrvmoFL0/UiqttyAhjx/3Rt5WBIM5HyWEE36g8ASl/glf8a4ajIhe6UHfnDbmcbC7g1AapWMA4JjF3m+xV1+oZrVIchjLjOmJGCgwUuHDvt7fwQ1hElkegMA7sGveNOwoYC9kZmPcX2PtRgnA04kCdEHGwXIYVkNAM4y+NBBOK5X4k/r81nul1K+pXEy7dz6aLSzSYUheWaiDofLb6cWNR6zTQ30O18QB9i5xBxbujEf8LJjjGXIrrOQpePmoPGfuytL5SfXLxVnBKsFOLKX6jUKLiiypsggkBeYkdRL5GB2LBJPmSH3TahHlcf341x2Wrc7PnLnyXM5Jqd6mT4Q0QHTkvDD27X2rcZXrRMyaCvX/aJOKpNwQdPwLdhOPHdgDB7inic9vBEhdIjCAsThuEtwhekjiM9zzjPPWa2bmIvw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR03MB4973.eurprd03.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(376002)(39850400004)(396003)(366004)(346002)(136003)(316002)(54906003)(38100700002)(2616005)(186003)(36756003)(2906002)(6506007)(38350700002)(26005)(1076003)(86362001)(110136005)(5660300002)(6666004)(6512007)(66476007)(4326008)(8676002)(7416002)(44832011)(66556008)(52116002)(83380400001)(8936002)(66946007)(478600001)(6486002)(41300700001)(21314003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AQXlbxxT8lcqsJ0HOUL5sPsOJLLl1wS/ppPEb89e9NWO4oJSsQrJ0YVHszGbvu+V8a+z8c0CWdKplV3/uLW8vPD7iMxfSFIfohBGMwMRsSUgszNRWtcwQP/0ecCfdtZWVy06n8aQqDiI/C+/Gh0RR1wFKR5ManUocuqYbMMETkM0YO+RFuzEso783gcb780mCoRYaCrL3EC+L0YLeXE85/9ps+LcFj0ZA4MNzBuec4PtNH72iTXv1PKWu7f5+ccp3a1/MkBF6y/5jH+WWiqyRdYDGz3+bZpEbq9GoS8eCov4r/lC4Zs6kSlMCdIrWYT/JVLnEIgLHEaegU6gEJhLa6Q+V9Bfrgqsf+jdpm8pXWJF5xR8Mh3EQ/RG3zFvJMF0yys6TsQ1nQoMg1oEsnAXayXL398j5DH3IwZ4KDWQjBmI5HgiNx372QqB8bVFGSQMYSJ8/dixUfQ4M6VnE6yVd6AnTWvxqBHnwc5DZ7v8QUm5WEUoIq0EqmDAi5ZJI09kSwIaqG0xRzcU54ixbcpanN23Q7WfamF0PUnnyJy6FGvCbYr1i7X8tZpdJbii2DSLKIv7Tlyl+uhNsKk9iVDioCXbYmE4JWt1bxfyifY1aKBnX0mZUbmWD4DPVNDzNa7rweyY9bOPRkJ134U4sCyV4fbzePh+nWEB8eD7h+nTuKXjMeOdFuGPgzOhd7PdeJuSWID824LtMeAtahwpS4lUylJIjC/5Rvvr+UC90Uws6/9rrd9qVYfyu0Pps/TbBdcHjXuUGQ6bsaEgWqtT6+ameigCuhnBaXbP63/78isLjMvLp9E0hngiu2nKCL1XJ3asrokXUGZBLCwdm8Ckr5cM22QcMBXUbCRCkUsBUJK7zdRkSY59Fp64Wjw1v1igfneavU82ID7na2f2+oruD0OwWagxx60qw/Ns+DP0kfyhCKCPhk01hnOZj/HjD25z7dXG4NCNRVorUCP4Lne1dogFYdObQ2WcbHlZ4OAFmGsZ512qwgcOjQ9PoMRvHZK8hf10kKtJUZ/jiJKkDwkYXwVDSlhzKmNyq5G1ol2DvK4T061+q8hqoqP9onlgx6Tde02L9XTIn5VceuDkb0QnxUFsw1wM+0We2W3gztES2zJckaS/GXsO4SMyQz/Hr71wW3w96ARLHlcWEx88aYVbKhadNTusAAzQtwy5xWjMDm0tXWUtQqaWkGNKoS3nBajmhWyLSN195zbqOOT8OkiREUNyiC+1S5mkdwCHwLS3pwrEQMPECaHmZ+udFeRgwyso5xlLO216otWW5TBM/kLuRReWhY1w87Y+FNmpxbsq0DxWTgxpQAGOgCoauRwoPTAKLLUDiwT/JkYEvgDiySAVWdmQmerlH9GXnf0zDrWJImmT9hOeifanJCTapzkF5wVii+VsrZOWdDQZe3OCyMMdOAUBOTt08QmYgJu7IfJqsaMM1Kucfs5UEciDlZZu+/G+KKiHa/fuI4VgVMH+q+s3Tr/8uvEsWioAJway7KnHllSZRui4mSsF2+QO3qVzeAJcfnihHesBcmew9LcD1Wl2r5Tqa+KwaoCBfwaC+tZCtgBXhoLXXO5e21L6ENWNGyFeYiyu3ICs+x4PlVAF4BFPureufw== X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1a80fd86-61d7-4ebd-e632-08da66ada12c X-MS-Exchange-CrossTenant-AuthSource: VI1PR03MB4973.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2022 22:01:54.6733 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5aTP9iAET8B9ZrjqDfEVTcanUWa5c8neODiTL7aavuxFmdBHfdoU46s0sArlrESX2lG6LaN4WyGasW8qNrfiOg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR03MB2857 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds bindings for the SerDes devices. They are disabled by default to prevent any breakage on existing boards. Signed-off-by: Sean Anderson --- Changes in v3: - Describe modes in device tree Changes in v2: - Use one phy cell for SerDes1, since no lanes can be grouped - Disable SerDes by default to prevent breaking boards inadvertently. .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 179 ++++++++++++++++++ 1 file changed, 179 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 0085e83adf65..0b3765cad383 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -413,6 +413,185 @@ bportals: bman-portals@508000000 { ranges = <0x0 0x5 0x08000000 0x8000000>; }; + /* + * XXX: For SerDes1, lane A uses pins SD1_RX3_P/N! That is, the + * lane numbers and pin numbers are _reversed_. In addition, + * the PCCR documentation is _inconsistent_ in its usage of + * these terms! + * + * PCCR "Lane 0" refers to... + * ==== ===================== + * 0 Lane A + * 2 Lane A + * 8 Lane A + * 9 Lane A + * B Lane D! + */ + serdes1: phy@1ea0000 { + #clock-cells = <1>; + #phy-cells = <1>; + compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g"; + reg = <0x0 0x1ea0000 0x0 0x2000>; + status = "disabled"; + + pccr-0 { + fsl,pccr = <0x0>; + + /* PCIe.1 x1 */ + pcie-0 { + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,first-lane = <1>; + fsl,proto = "pcie"; + }; + }; + + pccr-8 { + fsl,pccr = <0x8>; + + /* SGMII.6 */ + sgmii-0 { + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,first-lane = <0>; + fsl,proto = "sgmii"; + }; + + /* SGMII.5 */ + sgmii-1 { + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,first-lane = <1>; + fsl,proto = "sgmii25"; + }; + + /* SGMII.10 */ + sgmii-2 { + fsl,index = <2>; + fsl,cfg = <0x1>; + fsl,first-lane = <2>; + fsl,proto = "sgmii25"; + }; + + /* SGMII.9 */ + sgmii-3 { + fsl,index = <3>; + fsl,cfg = <0x1>; + fsl,first-lane = <3>; + fsl,proto = "sgmii25"; + }; + }; + + pccr-9 { + fsl,pccr = <0x9>; + + /* QSGMII.6,5,10,1 */ + qsgmii-1 { + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,first-lane = <1>; + fsl,proto = "qsgmii"; + }; + }; + + pccr-b { + fsl,pccr = <0xb>; + + /* XFI.10 */ + xfi-0 { + fsl,index = <0>; + fsl,cfg = <0x2>; + fsl,first-lane = <2>; + fsl,proto = "xfi"; + }; + + /* XFI.9 */ + xfi-1 { + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,first-lane = <3>; + fsl,proto = "xfi"; + }; + }; + }; + + serdes2: phy@1eb0000 { + #clock-cells = <1>; + #phy-cells = <2>; + compatible = "fsl,ls1046a-serdes", "fsl,lynx-10g"; + reg = <0x0 0x1eb0000 0x0 0x2000>; + status = "disabled"; + + pccr-0 { + fsl,pccr = <0>; + + pcie-0 { + fsl,index = <0>; + fsl,proto = "pcie"; + + /* PCIe.1 x1 */ + cfg-1 { + fsl,cfg = <0x1>; + fsl,first-lane = <1>; + }; + + /* PCIe.1 x4 */ + cfg-3 { + fsl,cfg = <0x3>; + fsl,first-lane = <0>; + fsl,last-lane = <3>; + }; + }; + + pcie-2 { + fsl,index = <2>; + fsl,proto = "pcie"; + + /* PCIe.2 x1 */ + cfg-1 { + fsl,cfg = <0x1>; + fsl,first-lane = <2>; + }; + + /* PCIe.3 x2 */ + cfg-2 { + fsl,cfg = <0x2>; + fsl,first-lane = <2>; + fsl,last-lane = <3>; + }; + + /* PCIe.3 x1 */ + cfg-3 { + fsl,cfg = <0x3>; + fsl,first-lane = <3>; + }; + }; + }; + + pccr-2 { + fsl,pccr = <0x2>; + + sata-0 { + fsl,index = <0>; + fsl,cfg = <0x1>; + fsl,first-lane = <3>; + fsl,proto = "sata"; + }; + }; + + pccr-8 { + fsl,pccr = <0x8>; + + /* SGMII.2 */ + sgmii-1 { + fsl,index = <1>; + fsl,cfg = <0x1>; + fsl,first-lane = <1>; + fsl,proto = "sgmii"; + }; + }; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1046a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x1000>;