From patchwork Thu Jul 7 18:23:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 588259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8455C433EF for ; Thu, 7 Jul 2022 18:24:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236079AbiGGSYw (ORCPT ); Thu, 7 Jul 2022 14:24:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236078AbiGGSYt (ORCPT ); Thu, 7 Jul 2022 14:24:49 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B8AA2F3BF; Thu, 7 Jul 2022 11:24:48 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id s27so19973656pga.13; Thu, 07 Jul 2022 11:24:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6q8+tslNjj42is2Wq3LrKo5qrCaBaAPRJbMXgMdfGjQ=; b=DhBVZphbgje4AIE9scnB/AiBcqQMjgFpJ4KQH4530InyLm0RL1ySwkb6VD5YzvCgJW aMa81fA7aAvpVKSXu7BdCEJurulD5fEjQ6UOyS4A7j1EBS1FHfaermNEBg94BxKa6WBI 7AjbgtWR3wQ25ZaG05LRuktC9lmQOsCJBs8jewhAjURF93yVaAGfmBagrspZWdMFTe+k 8jOPda3rtbpO+tGMwoxZ15L/8AbpRE1/5FQSDRQxFoe0VeFCoCkzSoh1uyA1TdwA0InB +WTOPUWAdKvDjJo5nh4M7A6S3kXXfwFokox9XaLwCL0OZXF7oKsqc040aYzu/xtfF5Ud Ve6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6q8+tslNjj42is2Wq3LrKo5qrCaBaAPRJbMXgMdfGjQ=; b=vzgUvf4kx/Q/rs8pUUtdFyXTHrRRbpxL/MODBGLbPikIr7No2NRRT+SP6pqnA8d0CT Isub4TlaqU1qo8lUDNkz+ZzwgiWXtICjsIUWdYifvuuyHphougP8Cd727p9S4T0Cwvs6 trieuNFHL3oR3i9vfs6PiFk0ZUQ1U22torS9e4ofnykjt+rhFmc/vtkuOalQ9EXAnvAa mLmNiKz2+yM8QG80bcAGSR4/krxM0dwt/HXHMwB818a5Kjr29eCz9w0M8Lcc/da6KTAH zcPPxc3iyXPS77IpLONXytePk0+NQCM4TLkoZUR/lBNhypbby93hMGe3IRagVKQc9aPP kAww== X-Gm-Message-State: AJIora/5m1qUgmqrvl4HQgT2cHQu1bcJZuph7Cik1/pDph+n5jH6uOif TB9kBEJUOlMlK8nafIJJsIg= X-Google-Smtp-Source: AGRyM1uzxWGGMoYwsGhJojNPdBl+m6Z+wxbtxQsV/MrMoA+8ndxIvifQCIF8K4oucXDUtbumwFneHA== X-Received: by 2002:a63:1724:0:b0:412:7bee:fdba with SMTP id x36-20020a631724000000b004127beefdbamr12075693pgl.340.1657218287679; Thu, 07 Jul 2022 11:24:47 -0700 (PDT) Received: from prasmi.domain.name ([103.219.60.85]) by smtp.gmail.com with ESMTPSA id o12-20020a170902d4cc00b0016a3f9e4865sm28589279plg.148.2022.07.07.11.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 11:24:47 -0700 (PDT) From: prabhakar.csengg@gmail.com X-Google-Original-From: prabhakar.mahadev-lad.rj@bp.renesas.com To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar , Rob Herring Subject: [PATCH v8 2/6] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller Date: Thu, 7 Jul 2022 19:23:10 +0100 Message-Id: <20220707182314.66610-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220707182314.66610-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220707182314.66610-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Add DT bindings for the Renesas RZ/G2L Interrupt Controller. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- .../renesas,rzg2l-irqc.yaml | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml new file mode 100644 index 000000000000..ffbb4ab4d9a7 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55) + +maintainers: + - Lad Prabhakar + - Geert Uytterhoeven + +description: | + IA55 performs various interrupt controls including synchronization for the external + interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral + interrupts output by each IP. And it notifies the interrupt to the GIC + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts + - NMI edge select (NMI is not treated as NMI exception and supports fall edge and + stand-up edge detection interrupts) + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-irqc # RZ/G2L + - const: renesas,rzg2l-irqc + + '#interrupt-cells': + description: The first cell should contain external interrupt number (IRQ0-7) and the + second cell is used to specify the flag. + const: 2 + + '#address-cells': + const: 0 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 41 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: clk + - const: pclk + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; + reg = <0x110a0000 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_IA55_RESETN>; + };