From patchwork Mon Jul 4 10:00:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 587269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B71CCC43334 for ; Mon, 4 Jul 2022 10:01:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234100AbiGDKBI (ORCPT ); Mon, 4 Jul 2022 06:01:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234086AbiGDKAs (ORCPT ); Mon, 4 Jul 2022 06:00:48 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB573DF05; Mon, 4 Jul 2022 03:00:46 -0700 (PDT) X-UUID: ffd65cceb9d34fbc865e8de69de3d55c-20220704 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.7, REQID:3ef2b95f-f484-4e8b-8234-70389ef818c7, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:87442a2, CLOUDID:15925b63-0b3f-4b2c-b3a6-ed5c044366a0, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: ffd65cceb9d34fbc865e8de69de3d55c-20220704 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1739505395; Mon, 04 Jul 2022 18:00:32 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 4 Jul 2022 18:00:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 4 Jul 2022 18:00:30 +0800 From: Tinghan Shen To: Yong Wu , Joerg Roedel , Will Deacon , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chun-Jie Chen , AngeloGioacchino Del Regno , Enric Balletbo i Serra , Tinghan Shen , Weiyi Lu CC: , , , , , Subject: [PATCH v1 07/16] arm64: dts: mt8195: Add vdosys and vppsys clock nodes Date: Mon, 4 Jul 2022 18:00:19 +0800 Message-ID: <20220704100028.19932-8-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220704100028.19932-1-tinghan.shen@mediatek.com> References: <20220704100028.19932-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add display clock nodes. Signed-off-by: Tinghan Shen --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 900aaa16f862..8d59a7da3271 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -983,6 +983,12 @@ #clock-cells = <1>; }; + vppsys0: clock-controller@14000000 { + compatible = "mediatek,mt8195-vppsys0"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + wpesys: clock-controller@14e00000 { compatible = "mediatek,mt8195-wpesys"; reg = <0 0x14e00000 0 0x1000>; @@ -1001,6 +1007,12 @@ #clock-cells = <1>; }; + vppsys1: clock-controller@14f00000 { + compatible = "mediatek,mt8195-vppsys1"; + reg = <0 0x14f00000 0 0x1000>; + #clock-cells = <1>; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8195-imgsys"; reg = <0 0x15000000 0 0x1000>; @@ -1108,5 +1120,17 @@ reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; + + vdosys0: syscon@1c01a000 { + compatible = "mediatek,mt8195-mmsys", "syscon"; + reg = <0 0x1c01a000 0 0x1000>; + #clock-cells = <1>; + }; + + vdosys1: syscon@1c100000 { + compatible = "mediatek,mt8195-mmsys", "syscon"; + reg = <0 0x1c100000 0 0x1000>; + #clock-cells = <1>; + }; }; };