From patchwork Sun Jul 3 10:47:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 586945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87665C43334 for ; Sun, 3 Jul 2022 10:47:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232506AbiGCKrl (ORCPT ); Sun, 3 Jul 2022 06:47:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232377AbiGCKrc (ORCPT ); Sun, 3 Jul 2022 06:47:32 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A8CD7642C; Sun, 3 Jul 2022 03:47:25 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.92,241,1650898800"; d="scan'208";a="126488400" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 03 Jul 2022 19:47:24 +0900 Received: from localhost.localdomain (unknown [10.226.92.2]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 90B10427AC5C; Sun, 3 Jul 2022 19:47:19 +0900 (JST) From: Biju Das To: Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski Cc: Biju Das , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Uwe_Kleine-K?= =?utf-8?q?=C3=B6nig?= , Geert Uytterhoeven , Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 2/6] dt-bindings: can: nxp,sja1000: Document RZ/N1{D,S} support Date: Sun, 3 Jul 2022 11:47:01 +0100 Message-Id: <20220703104705.341070-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220703104705.341070-1-biju.das.jz@bp.renesas.com> References: <20220703104705.341070-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add CAN binding documentation for Renesas RZ/N1 SoC. The SJA1000 CAN controller on RZ/N1 SoC has some differences compared to others like it has no clock divider register (CDR) support and it has no HW loopback (HW doesn't see tx messages on rx), so introduced a new compatible 'renesas,rzn1-sja1000' to handle these differences. Signed-off-by: Biju Das --- v1->v2: * Updated commit description. * Added an example for RZ/N1D SJA1000 usage --- .../bindings/net/can/nxp,sja1000.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml index 3232ce7e2642..dca2c932df31 100644 --- a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml +++ b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml @@ -20,6 +20,15 @@ allOf: then: required: - reg-io-width + - if: + properties: + compatible: + contains: + const: renesas,rzn1-sja1000 + then: + required: + - clocks + - clock-names properties: compatible: @@ -28,6 +37,12 @@ properties: const: nxp,sja1000 - description: Technologic Systems SJA1000 CAN Controller const: technologic,sja1000 + - description: Renesas RZ/N1 SJA1000 CAN Controller + items: + - enum: + - renesas,r9a06g032-sja1000 # RZ/N1D + - renesas,r9a06g033-sja1000 # RZ/N1S + - const: renesas,rzn1-sja1000 # RZ/N1 reg: maxItems: 1 @@ -35,6 +50,12 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 1 + + clock-names: + const: can_clk + reg-io-width: $ref: /schemas/types.yaml#/definitions/uint32 description: I/O register width (in bytes) implemented by this device @@ -100,3 +121,16 @@ examples: interrupts = <1>; nxp,external-clock-frequency = <24000000>; }; + + - | + #include + #include + + can@52104000 { + compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000"; + reg = <0x52104000 0x800>; + reg-io-width = <4>; + interrupts = ; + clocks = <&sysctrl R9A06G032_HCLK_CAN0>; + clock-names = "can_clk"; + };