From patchwork Mon Jun 20 11:08:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 583444 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07D18C43334 for ; Mon, 20 Jun 2022 11:11:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241668AbiFTLLm (ORCPT ); Mon, 20 Jun 2022 07:11:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241389AbiFTLKn (ORCPT ); Mon, 20 Jun 2022 07:10:43 -0400 Received: from relay10.mail.gandi.net (relay10.mail.gandi.net [IPv6:2001:4b98:dc4:8::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F63315A2E; Mon, 20 Jun 2022 04:10:25 -0700 (PDT) Received: (Authenticated sender: clement.leger@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 2530924000E; Mon, 20 Jun 2022 11:10:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1655723423; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kCft54/wbUztXKT2urhOKH33tJlwwROSYaG1fJeAUws=; b=MFNm7RgnP6YTyHRSSYCEEIEhvj+snogpXl6FCn8UARKr5kkbSP/zK2NKJwjMDWWByadbWB RtehjoWFT2wRX4juOa+fiYtdpZ5UYX/JJpauLVqwfs3EYXIlO4hU/eCa+T4+CUSyz22OPQ yunJHen/XR3LmTcWtCdDqb8e/qdZA8+DKcPp+gYPlVBxCgDmxLDn16dTOxWOCfZqxo/gGB sUVjsT6s7Q0v6aKJ3Ori0EVuOFNJOZqJdkFg3uR7HGiB1MWm9QLe1ZVKM3o81J6qYJiRD5 y2JMkJJFelVxj1hvWTScsfA9Dc5OkMnuvC/bgeQSAvlM9EtotYOLF2VC1Js1Tg== From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Andrew Lunn , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Heiner Kallweit , Russell King , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Thomas Petazzoni , Herve Codina , =?utf-8?q?Miqu=C3=A8l_Raynal?= , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org Subject: [PATCH net-next v8 13/16] ARM: dts: r9a06g032: describe GMAC2 Date: Mon, 20 Jun 2022 13:08:43 +0200 Message-Id: <20220620110846.374787-14-clement.leger@bootlin.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220620110846.374787-1-clement.leger@bootlin.com> References: <20220620110846.374787-1-clement.leger@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org RZ/N1 SoC includes two MAC named GMACx that are compatible with the "snps,dwmac" driver. GMAC1 is connected directly to the MII converter port 1. GMAC2 however can be used as the MAC for the switch CPU management port or can be muxed to be connected directly to the MII converter port 2. This commit add description for the GMAC2 which will be used by the switch description. Signed-off-by: Clément Léger --- arch/arm/boot/dts/r9a06g032.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index f6241af33112..42ce02e51e8d 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -304,6 +304,24 @@ dma1: dma-controller@40105000 { data-width = <8>; }; + gmac2: ethernet@44002000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44002000 0x2000>; + interrupt-parent = <&gic>; + interrupts = , + , + ; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; + clock-names = "stmmaceth"; + power-domains = <&sysctrl>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + status = "disabled"; + }; + eth_miic: eth-miic@44030000 { compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; #address-cells = <1>;