From patchwork Thu Jun 16 18:23:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 582335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DBD8C43334 for ; Thu, 16 Jun 2022 18:24:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235967AbiFPSYO (ORCPT ); Thu, 16 Jun 2022 14:24:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232468AbiFPSYN (ORCPT ); Thu, 16 Jun 2022 14:24:13 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22E844B1EF for ; Thu, 16 Jun 2022 11:24:12 -0700 (PDT) Received: from pendragon.lan (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id F35B5DBF; Thu, 16 Jun 2022 20:24:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1655403850; bh=6zhorOMHMcApn1JCVBnoz1jaHDN+7f/JdyrBu4DYqwk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IzrHQr2Lo8z1eo+AiH6zpLqtkmmhD6axP+JKJBG4rZSBao/9VY+BGhtCm7I9gxQMq XSsRv0HAhybzNJWxpVcGwgyhIqGvxffwn5nAlxsDXyBo7jbZdA8iuabWntN5KcyrYZ He+8T9QGwsWrEAFD8a3q+VE4HwuuXYPA4nzORhq8= From: Laurent Pinchart To: libcamera-devel@lists.libcamera.org Cc: Sakari Ailus , Hans Verkuil , Jacopo Mondi , Xavier Roumegue , linux-imx@nxp.com, kernel@pengutronix.de, devicetree@vger.kernel.org, Rob Herring , Krzysztof Kozlowski Subject: [PATCH 6/7] dt-bindings: media: Add i.MX8 ISI DT bindings Date: Thu, 16 Jun 2022 21:23:49 +0300 Message-Id: <20220616182350.17352-7-laurent.pinchart@ideasonboard.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220616182350.17352-1-laurent.pinchart@ideasonboard.com> References: <20220616182350.17352-1-laurent.pinchart@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Image Sensing Interface (ISI) combines image processing pipelines with DMA engines to process and capture frames originating from a variety of sources. The inputs to the ISI go through Pixel Link interfaces, and their number and nature is SoC-dependent. They cover both capture interfaces (MIPI CSI-2 RX, HDMI RX) and memory inputs. Signed-off-by: Laurent Pinchart --- .../bindings/media/nxp,imx8-isi.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml diff --git a/Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml b/Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml new file mode 100644 index 000000000000..6812c66fa49d --- /dev/null +++ b/Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX8 Image Sensing Interface + +maintainers: + - Laurent Pinchart + +description: | + The Image Sensing Interface (ISI) combines image processing pipelines with + DMA engines to process and capture frames originating from a variety of + sources. The inputs to the ISI go through Pixel Link interfaces, and their + number and nature is SoC-dependent. They cover both capture interfaces (MIPI + CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. + +properties: + compatible: + enum: + - fsl,imx8mn-isi + - fsl,imx8mp-isi + + reg: + maxItems: 1 + + clocks: + items: + - description: The AXI clock + - description: The APB clock + # TODO: Check if the per-channel ipg_proc_clk clocks need to be specified + # as well, in case some SoCs have the ability to control them separately. + # This may be the case of the i.MX8[DQ]X(P) + + clock-names: + items: + - const: axi + - const: apb + + fsl,blk-ctrl: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle referencing the block control that contains the CSIS to ISI + gasket. + + power-domains: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Ports represent the Pixel Link inputs to the ISI. Their number and + assignment are model-dependent. Each port shall have a single endpoint. + + patternProperties: + "^port@[0-9]$": + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - fsl,blk-ctrl + - ports + +allOf: + - if: + properties: + compatible: + contains: + const: nxp,imx8mn-isi + then: + properties: + interrupts: + maxItems: 1 + ports: + properties: + port@0: + description: MIPI CSI-2 RX + required: + - port@0 + + - if: + properties: + compatible: + contains: + const: nxp,imx8mp-isi + then: + properties: + interrupts: + maxItems: 2 + ports: + properties: + port@0: + description: MIPI CSI-2 RX 0 + port@1: + description: MIPI CSI-2 RX 1 + required: + - port@0 + - port@1 + +additionalProperties: false + +examples: + - | + #include + #include + #include + + isi@32e00000 { + compatible = "fsl,imx8mp-isi"; + reg = <0x32e00000 0x4000>; + interrupts = , + ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&media_blk_ctrl>; + power-domains = <&mediamix_pd>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + isi_in_0: endpoint { + remote-endpoint = <&mipi_csi_0_out>; + }; + }; + + port@1 { + reg = <1>; + isi_in_1: endpoint { + remote-endpoint = <&mipi_csi_1_out>; + }; + }; + }; + }; + +...