diff --git a/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
new file mode 100644
index 000000000000..7be8a50269ec
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-usb4-5nm-qmp-combo.h
@@ -0,0 +1,1547 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
+#define PHY_QCOM_V5_5NM_QMP_COMBO_USB4_H
+
+/* USB4-USB3-DP Combo PHY register offsets */
+/* Module: USB43DP_COM_USB43DP_COM_USB4_USB3_DP_COM */
+#define USB43DP_V5_5NM_COM_PHY_MODE_CTRL				0x00
+#define USB43DP_V5_5NM_COM_SW_RESET					0x04
+#define USB43DP_V5_5NM_COM_POWER_DOWN_CTRL				0x08
+#define USB43DP_V5_5NM_COM_SWI_CTRL					0x0c
+#define USB43DP_V5_5NM_COM_TYPEC_CTRL					0x10
+#define USB43DP_V5_5NM_COM_TYPEC_PWRDN_CTRL				0x14
+#define USB43DP_V5_5NM_COM_DP_BIST_CFG_0				0x18
+#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL1				0x1c
+#define USB43DP_V5_5NM_COM_RESET_OVRD_CTRL2				0x20
+#define USB43DP_V5_5NM_COM_DBG_CLK_MUX_CTRL				0x24
+#define USB43DP_V5_5NM_COM_TYPEC_STATUS					0x28
+#define USB43DP_V5_5NM_COM_PLACEHOLDER_STATUS				0x2c
+#define USB43DP_V5_5NM_COM_REVISION_ID0					0x30
+#define USB43DP_V5_5NM_COM_REVISION_ID1					0x34
+#define USB43DP_V5_5NM_COM_REVISION_ID2					0x38
+#define USB43DP_V5_5NM_COM_REVISION_ID3					0x3c
+
+/* Module: USB43DP_DBGINT_USB43DP_DBGINT_USB3_PCS_DEBUG_INT */
+#define USB43DP_V5_5NM_DBGINT_INTGEN_STATUS1				0x00
+#define USB43DP_V5_5NM_DBGINT_INTGEN_STATUS2				0x04
+#define USB43DP_V5_5NM_DBGINT_CONFIG1					0x08
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG1			0x0c
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG2			0x10
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG3			0x14
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG4			0x18
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK1_CONFIG5			0x1c
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG1			0x20
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG2			0x24
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG3			0x28
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG4			0x2c
+#define USB43DP_V5_5NM_DBGINT_SIGNALBLK2_CONFIG5			0x30
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG1			0x34
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG2			0x38
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG3			0x3c
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG4			0x40
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK1_CONFIG5			0x44
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG1			0x48
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG2			0x4c
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG3			0x50
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG4			0x54
+#define USB43DP_V5_5NM_DBGINT_STRINGBLK2_CONFIG5			0x58
+
+/* Module: USB43DP_QSERDES_TXA_USB43DP_QSERDES_TXA_USB4_USB3_DP_QMP_TX */
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_MODE_LANENO			0x00
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_INVERT				0x04
+#define USB43DP_V5_5NM_QSERDES_TXA_CLKBUF_ENABLE			0x08
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_EMP_POST1_LVL			0x0c
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP		0x10
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_DRV_LVL				0x14
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_DRV_LVL_OFFSET			0x18
+#define USB43DP_V5_5NM_QSERDES_TXA_RESET_TSYNC_EN			0x1c
+#define USB43DP_V5_5NM_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN		0x20
+#define USB43DP_V5_5NM_QSERDES_TXA_LPB_EN				0x24
+#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_TX			0x28
+#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_RX			0x2c
+#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX		0x30
+#define USB43DP_V5_5NM_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX		0x34
+#define USB43DP_V5_5NM_QSERDES_TXA_PERL_LENGTH1				0x38
+#define USB43DP_V5_5NM_QSERDES_TXA_PERL_LENGTH2				0x3c
+#define USB43DP_V5_5NM_QSERDES_TXA_SERDES_BYP_EN_OUT			0x40
+#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS_SEL			0x44
+#define USB43DP_V5_5NM_QSERDES_TXA_TRANSCEIVER_BIAS_EN			0x48
+#define USB43DP_V5_5NM_QSERDES_TXA_HIGHZ_DRVR_EN			0x4c
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_POL_INV				0x50
+#define USB43DP_V5_5NM_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN		0x54
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN1			0x58
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN2			0x5c
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN3			0x60
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN4			0x64
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN5			0x68
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN6			0x6c
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN7			0x70
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_PATTERN8			0x74
+#define USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_1				0x78
+#define USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_2				0x7c
+#define USB43DP_V5_5NM_QSERDES_TXA_LANE_MODE_3				0x80
+#define USB43DP_V5_5NM_QSERDES_TXA_ATB_SEL1				0x84
+#define USB43DP_V5_5NM_QSERDES_TXA_ATB_SEL2				0x88
+#define USB43DP_V5_5NM_QSERDES_TXA_RCV_DETECT_LVL			0x8c
+#define USB43DP_V5_5NM_QSERDES_TXA_RCV_DETECT_LVL_2			0x90
+#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED1				0x94
+#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED2				0x98
+#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED3				0x9c
+#define USB43DP_V5_5NM_QSERDES_TXA_PRBS_SEED4				0xa0
+#define USB43DP_V5_5NM_QSERDES_TXA_RESET_GEN				0xa4
+#define USB43DP_V5_5NM_QSERDES_TXA_RESET_GEN_MUXES			0xa8
+#define USB43DP_V5_5NM_QSERDES_TXA_TRAN_DRVR_EMP_EN			0xac
+#define USB43DP_V5_5NM_QSERDES_TXA_VMODE_CTRL1				0xb0
+#define USB43DP_V5_5NM_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1			0xb4
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_STATUS				0xb8
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_ERROR_COUNT1			0xbc
+#define USB43DP_V5_5NM_QSERDES_TXA_BIST_ERROR_COUNT2			0xc0
+#define USB43DP_V5_5NM_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1		0xc4
+#define USB43DP_V5_5NM_QSERDES_TXA_LANE_DIG_CONFIG			0xc8
+#define USB43DP_V5_5NM_QSERDES_TXA_PI_QEC_CTRL				0xcc
+#define USB43DP_V5_5NM_QSERDES_TXA_PRE_EMPH				0xd0
+#define USB43DP_V5_5NM_QSERDES_TXA_SW_RESET				0xd4
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_BAND				0xd8
+#define USB43DP_V5_5NM_QSERDES_TXA_SLEW_CNTL0				0xdc
+#define USB43DP_V5_5NM_QSERDES_TXA_SLEW_CNTL1				0xe0
+#define USB43DP_V5_5NM_QSERDES_TXA_INTERFACE_SELECT			0xe4
+#define USB43DP_V5_5NM_QSERDES_TXA_DIG_BKUP_CTRL			0xe8
+#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS0				0xec
+#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS1				0xf0
+#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS2				0xf4
+#define USB43DP_V5_5NM_QSERDES_TXA_DEBUG_BUS3				0xf8
+#define USB43DP_V5_5NM_QSERDES_TXA_TX_BKUP_RO_BUS			0xfc
+
+/* Module: USB43DP_QSERDES_RXA_USB43DP_QSERDES_RXA_USB4_USB3_DP_QMP_RX */
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE0		0x000
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE1		0x004
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE2		0x008
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE3		0x00c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE0		0x010
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE1		0x014
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE2		0x018
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE3		0x01c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_SATURATION			0x020
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_TO_SO_DELAY			0x024
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE0	0x028
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE0	0x02c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE1	0x030
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE1	0x034
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE2	0x038
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE2	0x03c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE3	0x040
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE3	0x044
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PI_CTRL1			0x048
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PI_CTRL2			0x04c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE0		0x050
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE1		0x054
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE2		0x058
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH1_RATE3		0x05c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE0		0x060
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE1		0x064
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE2		0x068
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_THRESH2_RATE3		0x06c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE0			0x070
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE1			0x074
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE2			0x078
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN1_RATE3			0x07c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE0			0x080
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE1			0x084
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2			0x088
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SB2_GAIN2_RATE3			0x08c
+#define USB43DP_V5_5NM_QSERDES_RXA_RXCLK_DIV2_CTRL			0x090
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BAND				0x094
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_TERM_BW				0x098
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE0			0x09c
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE1			0x0a0
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE2			0x0a4
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_FO_GAIN_RATE3			0x0a8
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE0			0x0ac
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE1			0x0b0
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE2			0x0b4
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_GAIN_RATE3			0x0b8
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PI_CONTROLS			0x0bc
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_PD_DATA_FILTER_ENABLES		0x0c0
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE0	0x0c4
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE1	0x0c8
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE2	0x0cc
+#define USB43DP_V5_5NM_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE3	0x0d0
+#define USB43DP_V5_5NM_QSERDES_RXA_AUX_CONTROL				0x0d4
+#define USB43DP_V5_5NM_QSERDES_RXA_AUXDATA_TB				0x0d8
+#define USB43DP_V5_5NM_QSERDES_RXA_RCLK_AUXDATA_SEL			0x0dc
+#define USB43DP_V5_5NM_QSERDES_RXA_EOM_CTRL				0x0e0
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_ENABLE			0x0e4
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_INITP			0x0e8
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_INITN			0x0ec
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_LVL				0x0f0
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_MODE				0x0f4
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_RESET			0x0f8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_RCVR_IQ_EN			0x0fc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_Q_EN_RATES			0x100
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I0_DC_OFFSETS		0x104
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I0BAR_DC_OFFSETS		0x108
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I1_DC_OFFSETS		0x10c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_I1BAR_DC_OFFSETS		0x110
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS			0x114
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS		0x118
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS			0x11c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS		0x120
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_EN				0x124
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_ENABLES			0x128
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_SIGN				0x12c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE		0x130
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CTRL1			0x134
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_CAL_CTRL2			0x138
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET		0x13c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE		0x140
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_HIGHZ_PARRATE			0x144
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET	0x148
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_1				0x14c
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_2				0x150
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_3				0x154
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_4				0x158
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP3_CTRL			0x15c
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP3_MANVAL_KTAP			0x160
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP4_CTRL			0x164
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP4_MANVAL_KTAP			0x168
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP5_CTRL			0x16c
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP5_MANVAL_KTAP			0x170
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADPT_CTRL				0x174
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_DAC_ENABLE1			0x178
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_DAC_ENABLE2			0x17c
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_PRE_THRESH1			0x180
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_PRE_THRESH2			0x184
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_POST_THRESH1		0x188
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_POST_THRESH2		0x18c
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_MAIN_THRESH1		0x190
+#define USB43DP_V5_5NM_QSERDES_RXA_TX_ADAPT_MAIN_THRESH2		0x194
+#define USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_CNTRL1			0x198
+#define USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_CNTRL2			0x19c
+#define USB43DP_V5_5NM_QSERDES_RXA_VGA_CAL_MAN_VAL			0x1a0
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_CNTRL1			0x1a4
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_CNTRL2			0x1a8
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE0		0x1ac
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE1		0x1b0
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE2		0x1b4
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE3		0x1b8
+#define USB43DP_V5_5NM_QSERDES_RXA_GM_CAL				0x1bc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_VGA_GAIN2_BLK1			0x1c0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_VGA_GAIN2_BLK2			0x1c4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2		0x1c8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3		0x1cc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4		0x1d0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_IDAC_TSETTLE_LOW			0x1d4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQ_OFFSET_LSB			0x1d8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQ_OFFSET_MSB			0x1dc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x1e0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2		0x1e4
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_ENABLES			0x1e8
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_CNTRL				0x1ec
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_LVL				0x1f0
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL		0x1f4
+#define USB43DP_V5_5NM_QSERDES_RXA_CDR_FREEZE_UP_DN			0x1f8
+#define USB43DP_V5_5NM_QSERDES_RXA_CDR_RESET_OVERRIDE			0x1fc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_INTERFACE_MODE			0x200
+#define USB43DP_V5_5NM_QSERDES_RXA_JITTER_GEN_MODE			0x204
+#define USB43DP_V5_5NM_QSERDES_RXA_SJ_AMP1				0x208
+#define USB43DP_V5_5NM_QSERDES_RXA_SJ_AMP2				0x20c
+#define USB43DP_V5_5NM_QSERDES_RXA_SJ_PER1				0x210
+#define USB43DP_V5_5NM_QSERDES_RXA_SJ_PER2				0x214
+#define USB43DP_V5_5NM_QSERDES_RXA_PPM_OFFSET1				0x218
+#define USB43DP_V5_5NM_QSERDES_RXA_PPM_OFFSET2				0x21c
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGN_PPM_PERIOD1			0x220
+#define USB43DP_V5_5NM_QSERDES_RXA_SIGN_PPM_PERIOD2			0x224
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B0			0x228
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B1			0x22c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B2			0x230
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B3			0x234
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B4			0x238
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B5			0x23c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B6			0x240
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE_0_1_B7			0x244
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B0			0x248
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B1			0x24c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B2			0x250
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B3			0x254
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B4			0x258
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B5			0x25c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B6			0x260
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE2_B7			0x264
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B0			0x268
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B1			0x26c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B2			0x270
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B3			0x274
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B4			0x278
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B5			0x27c
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B6			0x280
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MODE_RATE3_B7			0x284
+#define USB43DP_V5_5NM_QSERDES_RXA_PHPRE_CTRL				0x288
+#define USB43DP_V5_5NM_QSERDES_RXA_PHPRE_INITVAL			0x28c
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_EN_TIMER				0x290
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET		0x294
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CTRL1				0x298
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CTRL2				0x29c
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_OFFSET				0x2a0
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CMUX_POSTCAL_OFFSET		0x2a4
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CMUX_CAL_CTRL1			0x2a8
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CMUX_CAL_CTRL2			0x2ac
+#define USB43DP_V5_5NM_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1			0x2b0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL1			0x2b4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL2			0x2b8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL3			0x2bc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CTRL_4			0x2c0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CFG_RATE_0_1			0x2c4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_CFG_RATE_2_3			0x2c8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_CTRL1			0x2cc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_CTRL2			0x2d0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH1_RATE210	0x2d4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH1_RATE3		0x2d8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH2_RATE210	0x2dc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH2_RATE3		0x2e0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH3_RATE210	0x2e4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH3_RATE3		0x2e8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH4_RATE210	0x2ec
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH4_RATE3		0x2f0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH5_RATE210	0x2f4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH5_RATE3		0x2f8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH6_RATE210	0x2fc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH6_RATE3		0x300
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH7_RATE210	0x304
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_THRESH7_RATE3		0x308
+#define USB43DP_V5_5NM_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE10		0x30c
+#define USB43DP_V5_5NM_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32		0x310
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_VERTICAL_CTRL		0x314
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_VERTICAL_CODE		0x318
+#define USB43DP_V5_5NM_QSERDES_RXA_RES_CODE_THRESH_HIGH_AND_BYP		0x31c
+#define USB43DP_V5_5NM_QSERDES_RXA_RES_CODE_THRESH_LOW			0x320
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_CTRL1			0x324
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_CTRL2			0x328
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_CTRL3			0x32c
+#define USB43DP_V5_5NM_QSERDES_RXA_PI_CTRL1				0x330
+#define USB43DP_V5_5NM_QSERDES_RXA_PI_CTRL2				0x334
+#define USB43DP_V5_5NM_QSERDES_RXA_PI_QUAD				0x338
+#define USB43DP_V5_5NM_QSERDES_RXA_QPI_CTRL1				0x33c
+#define USB43DP_V5_5NM_QSERDES_RXA_QPI_CTRL2				0x340
+#define USB43DP_V5_5NM_QSERDES_RXA_QPI_QUAD				0x344
+#define USB43DP_V5_5NM_QSERDES_RXA_IDATA1				0x348
+#define USB43DP_V5_5NM_QSERDES_RXA_IDATA2				0x34c
+#define USB43DP_V5_5NM_QSERDES_RXA_IDATA3				0x350
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_OUTP				0x354
+#define USB43DP_V5_5NM_QSERDES_RXA_AC_JTAG_OUTN				0x358
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_SIGDET				0x35c
+#define USB43DP_V5_5NM_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1		0x360
+#define USB43DP_V5_5NM_QSERDES_RXA_READ_EQCODE				0x364
+#define USB43DP_V5_5NM_QSERDES_RXA_READ_OFFSETCODE			0x368
+#define USB43DP_V5_5NM_QSERDES_RXA_IA_ERROR_COUNTER_LOW			0x36c
+#define USB43DP_V5_5NM_QSERDES_RXA_IA_ERROR_COUNTER_HIGH		0x370
+#define USB43DP_V5_5NM_QSERDES_RXA_VGA_READ_CODE			0x374
+#define USB43DP_V5_5NM_QSERDES_RXA_VTHRESH_READ_CODE			0x378
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP1_READ_CODE			0x37c
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP2_READ_CODE			0x380
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP3_READ_CODE			0x384
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP4_READ_CODE			0x388
+#define USB43DP_V5_5NM_QSERDES_RXA_DFE_TAP5_READ_CODE			0x38c
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I0			0x390
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I0BAR			0x394
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I1			0x398
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_I1BAR			0x39c
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_Q			0x3a0
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_QBAR			0x3a4
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_A			0x3a8
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_ABAR			0x3ac
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_SM_ON			0x3b0
+#define USB43DP_V5_5NM_QSERDES_RXA_IDAC_STATUS_SIGNERROR		0x3b4
+#define USB43DP_V5_5NM_QSERDES_RXA_IVCM_CAL_STATUS			0x3b8
+#define USB43DP_V5_5NM_QSERDES_RXA_IVCM_CAL_DEBUG_STATUS		0x3bc
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_CAL_STATUS			0x3c0
+#define USB43DP_V5_5NM_QSERDES_RXA_DCC_READ_CODE_STATUS			0x3c4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_DEBUG1_STATUS		0x3c8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_DEBUG2_STATUS		0x3cc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_READ_CODE_STATUS		0x3d0
+#define USB43DP_V5_5NM_QSERDES_RXA_EOM_ERR_CNT_LSB_STATUS		0x3d4
+#define USB43DP_V5_5NM_QSERDES_RXA_EOM_ERR_CNT_MSB_STATUS		0x3d8
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_MARG_COARSE_TUNE_STATUS		0x3dc
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS1_STATUS		0x3e0
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS2_STATUS		0x3e4
+#define USB43DP_V5_5NM_QSERDES_RXA_RX_BKUP_READ_BUS3_STATUS		0x3e8
+
+/* Module: USB43DP_QSERDES_TXB_USB43DP_QSERDES_TXB_USB4_USB3_DP_QMP_TX */
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_MODE_LANENO			0x00
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_INVERT				0x04
+#define USB43DP_V5_5NM_QSERDES_TXB_CLKBUF_ENABLE			0x08
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_EMP_POST1_LVL			0x0c
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP		0x10
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_DRV_LVL				0x14
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_DRV_LVL_OFFSET			0x18
+#define USB43DP_V5_5NM_QSERDES_TXB_RESET_TSYNC_EN			0x1c
+#define USB43DP_V5_5NM_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN		0x20
+#define USB43DP_V5_5NM_QSERDES_TXB_LPB_EN				0x24
+#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_TX			0x28
+#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_RX			0x2c
+#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX		0x30
+#define USB43DP_V5_5NM_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX		0x34
+#define USB43DP_V5_5NM_QSERDES_TXB_PERL_LENGTH1				0x38
+#define USB43DP_V5_5NM_QSERDES_TXB_PERL_LENGTH2				0x3c
+#define USB43DP_V5_5NM_QSERDES_TXB_SERDES_BYP_EN_OUT			0x40
+#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS_SEL			0x44
+#define USB43DP_V5_5NM_QSERDES_TXB_TRANSCEIVER_BIAS_EN			0x48
+#define USB43DP_V5_5NM_QSERDES_TXB_HIGHZ_DRVR_EN			0x4c
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_POL_INV				0x50
+#define USB43DP_V5_5NM_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN		0x54
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN1			0x58
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN2			0x5c
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN3			0x60
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN4			0x64
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN5			0x68
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN6			0x6c
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN7			0x70
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_PATTERN8			0x74
+#define USB43DP_V5_5NM_QSERDES_TXB_LANE_MODE_1				0x78
+#define USB43DP_V5_5NM_QSERDES_TXB_LANE_MODE_2				0x7c
+#define USB43DP_V5_5NM_QSERDES_TXB_LANE_MODE_3				0x80
+#define USB43DP_V5_5NM_QSERDES_TXB_ATB_SEL1				0x84
+#define USB43DP_V5_5NM_QSERDES_TXB_ATB_SEL2				0x88
+#define USB43DP_V5_5NM_QSERDES_TXB_RCV_DETECT_LVL			0x8c
+#define USB43DP_V5_5NM_QSERDES_TXB_RCV_DETECT_LVL_2			0x90
+#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED1				0x94
+#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED2				0x98
+#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED3				0x9c
+#define USB43DP_V5_5NM_QSERDES_TXB_PRBS_SEED4				0xa0
+#define USB43DP_V5_5NM_QSERDES_TXB_RESET_GEN				0xa4
+#define USB43DP_V5_5NM_QSERDES_TXB_RESET_GEN_MUXES			0xa8
+#define USB43DP_V5_5NM_QSERDES_TXB_TRAN_DRVR_EMP_EN			0xac
+#define USB43DP_V5_5NM_QSERDES_TXB_VMODE_CTRL1				0xb0
+#define USB43DP_V5_5NM_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1			0xb4
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_STATUS				0xb8
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_ERROR_COUNT1			0xbc
+#define USB43DP_V5_5NM_QSERDES_TXB_BIST_ERROR_COUNT2			0xc0
+#define USB43DP_V5_5NM_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1		0xc4
+#define USB43DP_V5_5NM_QSERDES_TXB_LANE_DIG_CONFIG			0xc8
+#define USB43DP_V5_5NM_QSERDES_TXB_PI_QEC_CTRL				0xcc
+#define USB43DP_V5_5NM_QSERDES_TXB_PRE_EMPH				0xd0
+#define USB43DP_V5_5NM_QSERDES_TXB_SW_RESET				0xd4
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_BAND				0xd8
+#define USB43DP_V5_5NM_QSERDES_TXB_SLEW_CNTL0				0xdc
+#define USB43DP_V5_5NM_QSERDES_TXB_SLEW_CNTL1				0xe0
+#define USB43DP_V5_5NM_QSERDES_TXB_INTERFACE_SELECT			0xe4
+#define USB43DP_V5_5NM_QSERDES_TXB_DIG_BKUP_CTRL			0xe8
+#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS0				0xec
+#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS1				0xf0
+#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS2				0xf4
+#define USB43DP_V5_5NM_QSERDES_TXB_DEBUG_BUS3				0xf8
+#define USB43DP_V5_5NM_QSERDES_TXB_TX_BKUP_RO_BUS			0xfc
+
+/* Module: USB43DP_QSERDES_RXB_USB43DP_QSERDES_RXB_USB4_USB3_DP_QMP_RX */
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE0		0x000
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE1		0x004
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE2		0x008
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE3		0x00c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE0		0x010
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE1		0x014
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE2		0x018
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE3		0x01c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_SATURATION			0x020
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_TO_SO_DELAY			0x024
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE0	0x028
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE0	0x02c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE1	0x030
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE1	0x034
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE2	0x038
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE2	0x03c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE3	0x040
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE3	0x044
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PI_CTRL1			0x048
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PI_CTRL2			0x04c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE0		0x050
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE1		0x054
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE2		0x058
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH1_RATE3		0x05c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE0		0x060
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE1		0x064
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE2		0x068
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_THRESH2_RATE3		0x06c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE0			0x070
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE1			0x074
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE2			0x078
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN1_RATE3			0x07c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE0			0x080
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE1			0x084
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2			0x088
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SB2_GAIN2_RATE3			0x08c
+#define USB43DP_V5_5NM_QSERDES_RXB_RXCLK_DIV2_CTRL			0x090
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BAND				0x094
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_TERM_BW				0x098
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE0			0x09c
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE1			0x0a0
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE2			0x0a4
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_FO_GAIN_RATE3			0x0a8
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE0			0x0ac
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE1			0x0b0
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE2			0x0b4
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_GAIN_RATE3			0x0b8
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PI_CONTROLS			0x0bc
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_PD_DATA_FILTER_ENABLES		0x0c0
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE0	0x0c4
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE1	0x0c8
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE2	0x0cc
+#define USB43DP_V5_5NM_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE3	0x0d0
+#define USB43DP_V5_5NM_QSERDES_RXB_AUX_CONTROL				0x0d4
+#define USB43DP_V5_5NM_QSERDES_RXB_AUXDATA_TB				0x0d8
+#define USB43DP_V5_5NM_QSERDES_RXB_RCLK_AUXDATA_SEL			0x0dc
+#define USB43DP_V5_5NM_QSERDES_RXB_EOM_CTRL				0x0e0
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_ENABLE			0x0e4
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_INITP			0x0e8
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_INITN			0x0ec
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_LVL				0x0f0
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_MODE				0x0f4
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_RESET			0x0f8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_RCVR_IQ_EN			0x0fc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_Q_EN_RATES			0x100
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I0_DC_OFFSETS		0x104
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I0BAR_DC_OFFSETS		0x108
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I1_DC_OFFSETS		0x10c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_I1BAR_DC_OFFSETS		0x110
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS			0x114
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS		0x118
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS			0x11c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS		0x120
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_EN				0x124
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_ENABLES			0x128
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_SIGN				0x12c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE		0x130
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_CAL_CTRL1			0x134
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_CAL_CTRL2			0x138
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET		0x13c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE		0x140
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_HIGHZ_PARRATE			0x144
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET	0x148
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_1				0x14c
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_2				0x150
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_3				0x154
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_4				0x158
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP3_CTRL			0x15c
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP3_MANVAL_KTAP			0x160
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP4_CTRL			0x164
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP4_MANVAL_KTAP			0x168
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP5_CTRL			0x16c
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP5_MANVAL_KTAP			0x170
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADPT_CTRL				0x174
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_DAC_ENABLE1			0x178
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_DAC_ENABLE2			0x17c
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_PRE_THRESH1			0x180
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_PRE_THRESH2			0x184
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_POST_THRESH1		0x188
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_POST_THRESH2		0x18c
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_MAIN_THRESH1		0x190
+#define USB43DP_V5_5NM_QSERDES_RXB_TX_ADAPT_MAIN_THRESH2		0x194
+#define USB43DP_V5_5NM_QSERDES_RXB_VGA_CAL_CNTRL1			0x198
+#define USB43DP_V5_5NM_QSERDES_RXB_VGA_CAL_CNTRL2			0x19c
+#define USB43DP_V5_5NM_QSERDES_RXB_VGA_CAL_MAN_VAL			0x1a0
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_CNTRL1			0x1a4
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_CNTRL2			0x1a8
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE0		0x1ac
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE1		0x1b0
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE2		0x1b4
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE3		0x1b8
+#define USB43DP_V5_5NM_QSERDES_RXB_GM_CAL				0x1bc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_VGA_GAIN2_BLK1			0x1c0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_VGA_GAIN2_BLK2			0x1c4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2		0x1c8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3		0x1cc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4		0x1d0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_IDAC_TSETTLE_LOW			0x1d4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQ_OFFSET_LSB			0x1d8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQ_OFFSET_MSB			0x1dc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x1e0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2		0x1e4
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_ENABLES			0x1e8
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_CNTRL				0x1ec
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_LVL				0x1f0
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL		0x1f4
+#define USB43DP_V5_5NM_QSERDES_RXB_CDR_FREEZE_UP_DN			0x1f8
+#define USB43DP_V5_5NM_QSERDES_RXB_CDR_RESET_OVERRIDE			0x1fc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_INTERFACE_MODE			0x200
+#define USB43DP_V5_5NM_QSERDES_RXB_JITTER_GEN_MODE			0x204
+#define USB43DP_V5_5NM_QSERDES_RXB_SJ_AMP1				0x208
+#define USB43DP_V5_5NM_QSERDES_RXB_SJ_AMP2				0x20c
+#define USB43DP_V5_5NM_QSERDES_RXB_SJ_PER1				0x210
+#define USB43DP_V5_5NM_QSERDES_RXB_SJ_PER2				0x214
+#define USB43DP_V5_5NM_QSERDES_RXB_PPM_OFFSET1				0x218
+#define USB43DP_V5_5NM_QSERDES_RXB_PPM_OFFSET2				0x21c
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGN_PPM_PERIOD1			0x220
+#define USB43DP_V5_5NM_QSERDES_RXB_SIGN_PPM_PERIOD2			0x224
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B0			0x228
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B1			0x22c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B2			0x230
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B3			0x234
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B4			0x238
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B5			0x23c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B6			0x240
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE_0_1_B7			0x244
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B0			0x248
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B1			0x24c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B2			0x250
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B3			0x254
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B4			0x258
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B5			0x25c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B6			0x260
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE2_B7			0x264
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B0			0x268
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B1			0x26c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B2			0x270
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B3			0x274
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B4			0x278
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B5			0x27c
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B6			0x280
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MODE_RATE3_B7			0x284
+#define USB43DP_V5_5NM_QSERDES_RXB_PHPRE_CTRL				0x288
+#define USB43DP_V5_5NM_QSERDES_RXB_PHPRE_INITVAL			0x28c
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_EN_TIMER				0x290
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET		0x294
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CTRL1				0x298
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CTRL2				0x29c
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_OFFSET				0x2a0
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CMUX_POSTCAL_OFFSET		0x2a4
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CMUX_CAL_CTRL1			0x2a8
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CMUX_CAL_CTRL2			0x2ac
+#define USB43DP_V5_5NM_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1			0x2b0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL1			0x2b4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL2			0x2b8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL3			0x2bc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CTRL_4			0x2c0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CFG_RATE_0_1			0x2c4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_CFG_RATE_2_3			0x2c8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_CTRL1			0x2cc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_CTRL2			0x2d0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH1_RATE210	0x2d4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH1_RATE3		0x2d8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH2_RATE210	0x2dc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH2_RATE3		0x2e0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH3_RATE210	0x2e4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH3_RATE3		0x2e8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH4_RATE210	0x2ec
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH4_RATE3		0x2f0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH5_RATE210	0x2f4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH5_RATE3		0x2f8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH6_RATE210	0x2fc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH6_RATE3		0x300
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH7_RATE210	0x304
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_THRESH7_RATE3		0x308
+#define USB43DP_V5_5NM_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE10		0x30c
+#define USB43DP_V5_5NM_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32		0x310
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_VERTICAL_CTRL		0x314
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_VERTICAL_CODE		0x318
+#define USB43DP_V5_5NM_QSERDES_RXB_RES_CODE_THRESH_HIGH_AND_BYP		0x31c
+#define USB43DP_V5_5NM_QSERDES_RXB_RES_CODE_THRESH_LOW			0x320
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_CTRL1			0x324
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_CTRL2			0x328
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_CTRL3			0x32c
+#define USB43DP_V5_5NM_QSERDES_RXB_PI_CTRL1				0x330
+#define USB43DP_V5_5NM_QSERDES_RXB_PI_CTRL2				0x334
+#define USB43DP_V5_5NM_QSERDES_RXB_PI_QUAD				0x338
+#define USB43DP_V5_5NM_QSERDES_RXB_QPI_CTRL1				0x33c
+#define USB43DP_V5_5NM_QSERDES_RXB_QPI_CTRL2				0x340
+#define USB43DP_V5_5NM_QSERDES_RXB_QPI_QUAD				0x344
+#define USB43DP_V5_5NM_QSERDES_RXB_IDATA1				0x348
+#define USB43DP_V5_5NM_QSERDES_RXB_IDATA2				0x34c
+#define USB43DP_V5_5NM_QSERDES_RXB_IDATA3				0x350
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_OUTP				0x354
+#define USB43DP_V5_5NM_QSERDES_RXB_AC_JTAG_OUTN				0x358
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_SIGDET				0x35c
+#define USB43DP_V5_5NM_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1		0x360
+#define USB43DP_V5_5NM_QSERDES_RXB_READ_EQCODE				0x364
+#define USB43DP_V5_5NM_QSERDES_RXB_READ_OFFSETCODE			0x368
+#define USB43DP_V5_5NM_QSERDES_RXB_IA_ERROR_COUNTER_LOW			0x36c
+#define USB43DP_V5_5NM_QSERDES_RXB_IA_ERROR_COUNTER_HIGH		0x370
+#define USB43DP_V5_5NM_QSERDES_RXB_VGA_READ_CODE			0x374
+#define USB43DP_V5_5NM_QSERDES_RXB_VTHRESH_READ_CODE			0x378
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP1_READ_CODE			0x37c
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP2_READ_CODE			0x380
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP3_READ_CODE			0x384
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP4_READ_CODE			0x388
+#define USB43DP_V5_5NM_QSERDES_RXB_DFE_TAP5_READ_CODE			0x38c
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I0			0x390
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I0BAR			0x394
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I1			0x398
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_I1BAR			0x39c
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_Q			0x3a0
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_QBAR			0x3a4
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_A			0x3a8
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_ABAR			0x3ac
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_SM_ON			0x3b0
+#define USB43DP_V5_5NM_QSERDES_RXB_IDAC_STATUS_SIGNERROR		0x3b4
+#define USB43DP_V5_5NM_QSERDES_RXB_IVCM_CAL_STATUS			0x3b8
+#define USB43DP_V5_5NM_QSERDES_RXB_IVCM_CAL_DEBUG_STATUS		0x3bc
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_CAL_STATUS			0x3c0
+#define USB43DP_V5_5NM_QSERDES_RXB_DCC_READ_CODE_STATUS			0x3c4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_DEBUG1_STATUS		0x3c8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_DEBUG2_STATUS		0x3cc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_READ_CODE_STATUS		0x3d0
+#define USB43DP_V5_5NM_QSERDES_RXB_EOM_ERR_CNT_LSB_STATUS		0x3d4
+#define USB43DP_V5_5NM_QSERDES_RXB_EOM_ERR_CNT_MSB_STATUS		0x3d8
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_MARG_COARSE_TUNE_STATUS		0x3dc
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_READ_BUS1_STATUS		0x3e0
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_READ_BUS2_STATUS		0x3e4
+#define USB43DP_V5_5NM_QSERDES_RXB_RX_BKUP_READ_BUS3_STATUS		0x3e8
+
+/* Module: USB3_QSERDES_PLL_USB3_QSERDES_PLL_USB4_USB3_DP_QMP_PLL_20G */
+#define USB3_V5_5NM_QSERDES_PLL_ATB_SEL1				0x000
+#define USB3_V5_5NM_QSERDES_PLL_ATB_SEL2				0x004
+#define USB3_V5_5NM_QSERDES_PLL_FREQ_UPDATE				0x008
+#define USB3_V5_5NM_QSERDES_PLL_BG_TIMER				0x00c
+#define USB3_V5_5NM_QSERDES_PLL_SSC_EN_CENTER				0x010
+#define USB3_V5_5NM_QSERDES_PLL_SSC_ADJ_PER1				0x014
+#define USB3_V5_5NM_QSERDES_PLL_SSC_ADJ_PER2				0x018
+#define USB3_V5_5NM_QSERDES_PLL_SSC_PER1				0x01c
+#define USB3_V5_5NM_QSERDES_PLL_SSC_PER2				0x020
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE0			0x024
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE0			0x028
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE0			0x02c
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE1			0x030
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE1			0x034
+#define USB3_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE1			0x038
+#define USB3_V5_5NM_QSERDES_PLL_POST_DIV				0x03c
+#define USB3_V5_5NM_QSERDES_PLL_POST_DIV_MUX				0x040
+#define USB3_V5_5NM_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN			0x044
+#define USB3_V5_5NM_QSERDES_PLL_CLK_ENABLE1				0x048
+#define USB3_V5_5NM_QSERDES_PLL_SYS_CLK_CTRL				0x04c
+#define USB3_V5_5NM_QSERDES_PLL_SYSCLK_BUF_ENABLE			0x050
+#define USB3_V5_5NM_QSERDES_PLL_PLL_EN					0x054
+#define USB3_V5_5NM_QSERDES_PLL_PLL_IVCO				0x058
+#define USB3_V5_5NM_QSERDES_PLL_CMN_IETRIM				0x05c
+#define USB3_V5_5NM_QSERDES_PLL_CMN_IPTRIM				0x060
+#define USB3_V5_5NM_QSERDES_PLL_EP_CLOCK_DETECT_CTRL			0x064
+#define USB3_V5_5NM_QSERDES_PLL_SYSCLK_DET_COMP_STATUS			0x068
+#define USB3_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE0			0x06c
+#define USB3_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE1			0x070
+#define USB3_V5_5NM_QSERDES_PLL_CP_CTRL_MODE0				0x074
+#define USB3_V5_5NM_QSERDES_PLL_CP_CTRL_MODE1				0x078
+#define USB3_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE0				0x07c
+#define USB3_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE1				0x080
+#define USB3_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE0				0x084
+#define USB3_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE1				0x088
+#define USB3_V5_5NM_QSERDES_PLL_PLL_CNTRL				0x08c
+#define USB3_V5_5NM_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM			0x090
+#define USB3_V5_5NM_QSERDES_PLL_SYSCLK_EN_SEL				0x094
+#define USB3_V5_5NM_QSERDES_PLL_CML_SYSCLK_SEL				0x098
+#define USB3_V5_5NM_QSERDES_PLL_RESETSM_CNTRL				0x09c
+#define USB3_V5_5NM_QSERDES_PLL_RESETSM_CNTRL2				0x0a0
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP_EN				0x0a4
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP_CFG				0x0a8
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE0				0x0ac
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE0				0x0b0
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE1				0x0b4
+#define USB3_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE1				0x0b8
+#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MODE0				0x0bc
+#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE0			0x0c0
+#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MODE1				0x0c4
+#define USB3_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE1			0x0c8
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE0			0x0cc
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE0			0x0d0
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE0			0x0d4
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE1			0x0d8
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE1			0x0dc
+#define USB3_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE1			0x0e0
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_INITVAL			0x0e4
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_EN				0x0e8
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0			0x0ec
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0			0x0f0
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1			0x0f4
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1			0x0f8
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0			0x0fc
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1			0x100
+#define USB3_V5_5NM_QSERDES_PLL_VCOCAL_DEADMAN_CTRL			0x104
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_CTRL				0x108
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAP				0x10c
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE0				0x110
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE0				0x114
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE1				0x118
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE1				0x11c
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL1			0x120
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL2			0x124
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL1			0x128
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL2			0x12c
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL1			0x130
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL2			0x134
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER1				0x138
+#define USB3_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER2				0x13c
+#define USB3_V5_5NM_QSERDES_PLL_CMN_STATUS				0x140
+#define USB3_V5_5NM_QSERDES_PLL_RESET_SM_STATUS				0x144
+#define USB3_V5_5NM_QSERDES_PLL_RESTRIM_CODE_STATUS			0x148
+#define USB3_V5_5NM_QSERDES_PLL_PLLCAL_CODE1_STATUS			0x14c
+#define USB3_V5_5NM_QSERDES_PLL_PLLCAL_CODE2_STATUS			0x150
+#define USB3_V5_5NM_QSERDES_PLL_CLK_SELECT				0x154
+#define USB3_V5_5NM_QSERDES_PLL_HSCLK_SEL				0x158
+#define USB3_V5_5NM_QSERDES_PLL_HSCLK_HS_SWITCH_SEL			0x15c
+#define USB3_V5_5NM_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS		0x160
+#define USB3_V5_5NM_QSERDES_PLL_PLL_ANALOG				0x164
+#define USB3_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE0			0x168
+#define USB3_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE1			0x16c
+#define USB3_V5_5NM_QSERDES_PLL_SW_RESET				0x170
+#define USB3_V5_5NM_QSERDES_PLL_CORE_CLK_EN				0x174
+#define USB3_V5_5NM_QSERDES_PLL_C_READY_STATUS				0x178
+#define USB3_V5_5NM_QSERDES_PLL_CMN_CONFIG				0x17c
+#define USB3_V5_5NM_QSERDES_PLL_CMN_RATE_OVERRIDE			0x180
+#define USB3_V5_5NM_QSERDES_PLL_SVS_MODE_CLK_SEL			0x184
+#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS0				0x188
+#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS1				0x18c
+#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS2				0x190
+#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS3				0x194
+#define USB3_V5_5NM_QSERDES_PLL_DEBUG_BUS_SEL				0x198
+#define USB3_V5_5NM_QSERDES_PLL_CMN_MISC1				0x19c
+#define USB3_V5_5NM_QSERDES_PLL_CMN_MODE				0x1a0
+#define USB3_V5_5NM_QSERDES_PLL_CMN_MODE_CONTD				0x1a4
+#define USB3_V5_5NM_QSERDES_PLL_VCO_DC_LEVEL_CTRL			0x1a8
+#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0		0x1ac
+#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0		0x1b0
+#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1		0x1b4
+#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1		0x1b8
+#define USB3_V5_5NM_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL			0x1bc
+#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_CTRL_1			0x1c0
+#define USB3_V5_5NM_QSERDES_PLL_MODE_OPERATION_STATUS			0x1c4
+#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_1			0x1c8
+#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_2			0x1cc
+#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_3			0x1d0
+#define USB3_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_4			0x1d4
+#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC				0x1d8
+#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_2			0x1dc
+#define USB3_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_3			0x1e0
+
+/* Module: USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
+#define USB3_V5_5NM_PCS_MISC_TYPEC_CTRL					0x00
+#define USB3_V5_5NM_PCS_MISC_TYPEC_PWRDN_CTRL				0x04
+#define USB3_V5_5NM_PCS_MISC_PCS_MISC_CONFIG1				0x08
+#define USB3_V5_5NM_PCS_MISC_CLAMP_ENABLE				0x0c
+#define USB3_V5_5NM_PCS_MISC_TYPEC_STATUS				0x10
+#define USB3_V5_5NM_PCS_MISC_PLACEHOLDER_STATUS				0x14
+
+/* Module: USB3_PCS_LN_USB3_PCS_LN_USB3_PCS_LANE */
+#define USB3_V5_5NM_PCS_LN_PCS_STATUS1					0x00
+#define USB3_V5_5NM_PCS_LN_PCS_STATUS2					0x04
+#define USB3_V5_5NM_PCS_LN_PCS_STATUS2_CLEAR				0x08
+#define USB3_V5_5NM_PCS_LN_PCS_STATUS3					0x0c
+#define USB3_V5_5NM_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS			0x10
+#define USB3_V5_5NM_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS			0x14
+#define USB3_V5_5NM_PCS_LN_BIST_CHK_STATUS				0x18
+#define USB3_V5_5NM_PCS_LN_INSIG_SW_CTRL1				0x1c
+#define USB3_V5_5NM_PCS_LN_INSIG_MX_CTRL1				0x20
+#define USB3_V5_5NM_PCS_LN_OUTSIG_SW_CTRL1				0x24
+#define USB3_V5_5NM_PCS_LN_OUTSIG_MX_CTRL1				0x28
+#define USB3_V5_5NM_PCS_LN_TEST_CONTROL1				0x2c
+#define USB3_V5_5NM_PCS_LN_BIST_CTRL					0x30
+#define USB3_V5_5NM_PCS_LN_PRBS_SEED0					0x34
+#define USB3_V5_5NM_PCS_LN_PRBS_SEED1					0x38
+#define USB3_V5_5NM_PCS_LN_FIXED_PAT_CTRL				0x3c
+#define USB3_V5_5NM_PCS_LN_EQ_CONFIG					0x40
+#define USB3_V5_5NM_PCS_LN_TEST_CONTROL2				0x44
+#define USB3_V5_5NM_PCS_LN_TEST_CONTROL3				0x48
+
+/* Module: USB3_PCS_USB3_PCS_USB3_PCS */
+#define USB3_V5_5NM_PCS_SW_RESET					0x000
+#define USB3_V5_5NM_PCS_REVISION_ID0					0x004
+#define USB3_V5_5NM_PCS_REVISION_ID1					0x008
+#define USB3_V5_5NM_PCS_REVISION_ID2					0x00c
+#define USB3_V5_5NM_PCS_REVISION_ID3					0x010
+#define USB3_V5_5NM_PCS_PCS_STATUS1					0x014
+#define USB3_V5_5NM_PCS_PCS_STATUS2					0x018
+#define USB3_V5_5NM_PCS_PCS_STATUS3					0x01c
+#define USB3_V5_5NM_PCS_PCS_STATUS4					0x020
+#define USB3_V5_5NM_PCS_PCS_STATUS5					0x024
+#define USB3_V5_5NM_PCS_PCS_STATUS6					0x028
+#define USB3_V5_5NM_PCS_PCS_STATUS7					0x02c
+#define USB3_V5_5NM_PCS_DEBUG_BUS_0_STATUS				0x030
+#define USB3_V5_5NM_PCS_DEBUG_BUS_1_STATUS				0x034
+#define USB3_V5_5NM_PCS_DEBUG_BUS_2_STATUS				0x038
+#define USB3_V5_5NM_PCS_DEBUG_BUS_3_STATUS				0x03c
+#define USB3_V5_5NM_PCS_POWER_DOWN_CONTROL				0x040
+#define USB3_V5_5NM_PCS_START_CONTROL					0x044
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL1					0x048
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL2					0x04c
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL3					0x050
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL4					0x054
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL5					0x058
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL6					0x05c
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL7					0x060
+#define USB3_V5_5NM_PCS_INSIG_SW_CTRL8					0x064
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL1					0x068
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL2					0x06c
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL3					0x070
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL4					0x074
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL5					0x078
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL7					0x07c
+#define USB3_V5_5NM_PCS_INSIG_MX_CTRL8					0x080
+#define USB3_V5_5NM_PCS_OUTSIG_SW_CTRL1					0x084
+#define USB3_V5_5NM_PCS_OUTSIG_MX_CTRL1					0x088
+#define USB3_V5_5NM_PCS_CLAMP_ENABLE					0x08c
+#define USB3_V5_5NM_PCS_POWER_STATE_CONFIG1				0x090
+#define USB3_V5_5NM_PCS_POWER_STATE_CONFIG2				0x094
+#define USB3_V5_5NM_PCS_FLL_CNTRL1					0x098
+#define USB3_V5_5NM_PCS_FLL_CNTRL2					0x09c
+#define USB3_V5_5NM_PCS_FLL_CNT_VAL_L					0x0a0
+#define USB3_V5_5NM_PCS_FLL_CNT_VAL_H_TOL				0x0a4
+#define USB3_V5_5NM_PCS_FLL_MAN_CODE					0x0a8
+#define USB3_V5_5NM_PCS_TEST_CONTROL1					0x0ac
+#define USB3_V5_5NM_PCS_TEST_CONTROL2					0x0b0
+#define USB3_V5_5NM_PCS_TEST_CONTROL3					0x0b4
+#define USB3_V5_5NM_PCS_TEST_CONTROL4					0x0b8
+#define USB3_V5_5NM_PCS_TEST_CONTROL5					0x0bc
+#define USB3_V5_5NM_PCS_TEST_CONTROL6					0x0c0
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG1				0x0c4
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG2				0x0c8
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG3				0x0cc
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG4				0x0d0
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG5				0x0d4
+#define USB3_V5_5NM_PCS_LOCK_DETECT_CONFIG6				0x0d8
+#define USB3_V5_5NM_PCS_REFGEN_REQ_CONFIG1				0x0dc
+#define USB3_V5_5NM_PCS_REFGEN_REQ_CONFIG2				0x0e0
+#define USB3_V5_5NM_PCS_REFGEN_REQ_CONFIG3				0x0e4
+#define USB3_V5_5NM_PCS_BIST_CTRL					0x0e8
+#define USB3_V5_5NM_PCS_PRBS_POLY0					0x0ec
+#define USB3_V5_5NM_PCS_PRBS_POLY1					0x0f0
+#define USB3_V5_5NM_PCS_FIXED_PAT0					0x0f4
+#define USB3_V5_5NM_PCS_FIXED_PAT1					0x0f8
+#define USB3_V5_5NM_PCS_FIXED_PAT2					0x0fc
+#define USB3_V5_5NM_PCS_FIXED_PAT3					0x100
+#define USB3_V5_5NM_PCS_FIXED_PAT4					0x104
+#define USB3_V5_5NM_PCS_FIXED_PAT5					0x108
+#define USB3_V5_5NM_PCS_FIXED_PAT6					0x10c
+#define USB3_V5_5NM_PCS_FIXED_PAT7					0x110
+#define USB3_V5_5NM_PCS_FIXED_PAT8					0x114
+#define USB3_V5_5NM_PCS_FIXED_PAT9					0x118
+#define USB3_V5_5NM_PCS_FIXED_PAT10					0x11c
+#define USB3_V5_5NM_PCS_FIXED_PAT11					0x120
+#define USB3_V5_5NM_PCS_FIXED_PAT12					0x124
+#define USB3_V5_5NM_PCS_FIXED_PAT13					0x128
+#define USB3_V5_5NM_PCS_FIXED_PAT14					0x12c
+#define USB3_V5_5NM_PCS_FIXED_PAT15					0x130
+#define USB3_V5_5NM_PCS_TXMGN_CONFIG					0x134
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V0					0x138
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V1					0x13c
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V2					0x140
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V3					0x144
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V4					0x148
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V0_RS				0x14c
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V1_RS				0x150
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V2_RS				0x154
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V3_RS				0x158
+#define USB3_V5_5NM_PCS_G12S1_TXMGN_V4_RS				0x15c
+#define USB3_V5_5NM_PCS_G3S2_TXMGN_MAIN					0x160
+#define USB3_V5_5NM_PCS_G3S2_TXMGN_MAIN_RS				0x164
+#define USB3_V5_5NM_PCS_G12S1_TXDEEMPH_M6DB				0x168
+#define USB3_V5_5NM_PCS_G12S1_TXDEEMPH_M3P5DB				0x16c
+#define USB3_V5_5NM_PCS_G3S2_PRE_GAIN					0x170
+#define USB3_V5_5NM_PCS_G3S2_POST_GAIN					0x174
+#define USB3_V5_5NM_PCS_G3S2_PRE_POST_OFFSET				0x178
+#define USB3_V5_5NM_PCS_G3S2_PRE_GAIN_RS				0x17c
+#define USB3_V5_5NM_PCS_G3S2_POST_GAIN_RS				0x180
+#define USB3_V5_5NM_PCS_G3S2_PRE_POST_OFFSET_RS				0x184
+#define USB3_V5_5NM_PCS_RX_SIGDET_LVL					0x188
+#define USB3_V5_5NM_PCS_RX_SIGDET_DTCT_CNTRL				0x18c
+#define USB3_V5_5NM_PCS_RCVR_DTCT_DLY_P1U2_L				0x190
+#define USB3_V5_5NM_PCS_RCVR_DTCT_DLY_P1U2_H				0x194
+#define USB3_V5_5NM_PCS_RATE_SLEW_CNTRL1				0x198
+#define USB3_V5_5NM_PCS_RATE_SLEW_CNTRL2				0x19c
+#define USB3_V5_5NM_PCS_PWRUP_RESET_DLY_TIME_AUXCLK			0x1a0
+#define USB3_V5_5NM_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L			0x1a4
+#define USB3_V5_5NM_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H			0x1a8
+#define USB3_V5_5NM_PCS_TSYNC_RSYNC_TIME				0x1ac
+#define USB3_V5_5NM_PCS_RX_CONFIG					0x1b0
+#define USB3_V5_5NM_PCS_TSYNC_DLY_TIME					0x1b4
+#define USB3_V5_5NM_PCS_ELECIDLE_DLY_SEL				0x1b8
+#define USB3_V5_5NM_PCS_CMN_ACK_OUT_SEL					0x1bc
+#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG1				0x1c0
+#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG2				0x1c4
+#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG3				0x1c8
+#define USB3_V5_5NM_PCS_ALIGN_DETECT_CONFIG4				0x1cc
+#define USB3_V5_5NM_PCS_PCS_TX_RX_CONFIG				0x1d0
+#define USB3_V5_5NM_PCS_RX_IDLE_DTCT_CNTRL				0x1d4
+#define USB3_V5_5NM_PCS_RX_DCC_CAL_CONFIG				0x1d8
+#define USB3_V5_5NM_PCS_EQ_CONFIG1					0x1dc
+#define USB3_V5_5NM_PCS_EQ_CONFIG2					0x1e0
+#define USB3_V5_5NM_PCS_EQ_CONFIG3					0x1e4
+#define USB3_V5_5NM_PCS_EQ_CONFIG4					0x1E8
+#define USB3_V5_5NM_PCS_EQ_CONFIG5					0x1EC
+
+/* Module: USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */
+#define USB3_V5_5NM_PCS_USB3_POWER_STATE_CONFIG1			0x00
+#define USB3_V5_5NM_PCS_USB3_AUTONOMOUS_MODE_STATUS			0x04
+#define USB3_V5_5NM_PCS_USB3_AUTONOMOUS_MODE_CTRL			0x08
+#define USB3_V5_5NM_PCS_USB3_AUTONOMOUS_MODE_CTRL2			0x0c
+#define USB3_V5_5NM_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS		0x10
+#define USB3_V5_5NM_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR			0x14
+#define USB3_V5_5NM_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL			0x18
+#define USB3_V5_5NM_PCS_USB3_LFPS_TX_ECSTART				0x1c
+#define USB3_V5_5NM_PCS_USB3_LFPS_PER_TIMER_VAL				0x20
+#define USB3_V5_5NM_PCS_USB3_LFPS_TX_END_CNT_U3_START			0x24
+#define USB3_V5_5NM_PCS_USB3_LFPS_CONFIG1				0x28
+#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_LOCK_TIME			0x2c
+#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_WAIT_TIME			0x30
+#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_CTLE_TIME			0x34
+#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2			0x38
+#define USB3_V5_5NM_PCS_USB3_RXEQTRAINING_DFE_TIME_S2			0x3c
+#define USB3_V5_5NM_PCS_USB3_RCVR_DTCT_DLY_U3_L				0x40
+#define USB3_V5_5NM_PCS_USB3_RCVR_DTCT_DLY_U3_H				0x44
+#define USB3_V5_5NM_PCS_USB3_ARCVR_DTCT_EN_PERIOD			0x48
+#define USB3_V5_5NM_PCS_USB3_ARCVR_DTCT_CM_DLY				0x4c
+#define USB3_V5_5NM_PCS_USB3_TXONESZEROS_RUN_LENGTH			0x50
+#define USB3_V5_5NM_PCS_USB3_ALFPS_DEGLITCH_VAL				0x54
+#define USB3_V5_5NM_PCS_USB3_SIGDET_STARTUP_TIMER_VAL			0x58
+#define USB3_V5_5NM_PCS_USB3_TEST_CONTROL				0x5c
+#define USB3_V5_5NM_PCS_USB3_RXTERMINATION_DLY_SEL			0x60
+
+/* Module: DP_QSERDES_PLL_DP_QSERDES_PLL_USB4_USB3_DP_QMP_PLL */
+#define DP_V5_5NM_QSERDES_PLL_ATB_SEL1					0x000
+#define DP_V5_5NM_QSERDES_PLL_ATB_SEL2					0x004
+#define DP_V5_5NM_QSERDES_PLL_FREQ_UPDATE				0x008
+#define DP_V5_5NM_QSERDES_PLL_BG_TIMER					0x00c
+#define DP_V5_5NM_QSERDES_PLL_SSC_EN_CENTER				0x010
+#define DP_V5_5NM_QSERDES_PLL_SSC_ADJ_PER1				0x014
+#define DP_V5_5NM_QSERDES_PLL_SSC_ADJ_PER2				0x018
+#define DP_V5_5NM_QSERDES_PLL_SSC_PER1					0x01c
+#define DP_V5_5NM_QSERDES_PLL_SSC_PER2					0x020
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE0			0x024
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE0			0x028
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE0			0x02c
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE1			0x030
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE1			0x034
+#define DP_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE1			0x038
+#define DP_V5_5NM_QSERDES_PLL_POST_DIV					0x03c
+#define DP_V5_5NM_QSERDES_PLL_POST_DIV_MUX				0x040
+#define DP_V5_5NM_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN			0x044
+#define DP_V5_5NM_QSERDES_PLL_CLK_ENABLE1				0x048
+#define DP_V5_5NM_QSERDES_PLL_SYS_CLK_CTRL				0x04c
+#define DP_V5_5NM_QSERDES_PLL_SYSCLK_BUF_ENABLE				0x050
+#define DP_V5_5NM_QSERDES_PLL_PLL_EN					0x054
+#define DP_V5_5NM_QSERDES_PLL_PLL_IVCO					0x058
+#define DP_V5_5NM_QSERDES_PLL_CMN_IETRIM				0x05c
+#define DP_V5_5NM_QSERDES_PLL_CMN_IPTRIM				0x060
+#define DP_V5_5NM_QSERDES_PLL_EP_CLOCK_DETECT_CTRL			0x064
+#define DP_V5_5NM_QSERDES_PLL_SYSCLK_DET_COMP_STATUS			0x068
+#define DP_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE0				0x06c
+#define DP_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE1				0x070
+#define DP_V5_5NM_QSERDES_PLL_CP_CTRL_MODE0				0x074
+#define DP_V5_5NM_QSERDES_PLL_CP_CTRL_MODE1				0x078
+#define DP_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE0				0x07c
+#define DP_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE1				0x080
+#define DP_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE0				0x084
+#define DP_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE1				0x088
+#define DP_V5_5NM_QSERDES_PLL_PLL_CNTRL					0x08c
+#define DP_V5_5NM_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM			0x090
+#define DP_V5_5NM_QSERDES_PLL_SYSCLK_EN_SEL				0x094
+#define DP_V5_5NM_QSERDES_PLL_CML_SYSCLK_SEL				0x098
+#define DP_V5_5NM_QSERDES_PLL_RESETSM_CNTRL				0x09c
+#define DP_V5_5NM_QSERDES_PLL_RESETSM_CNTRL2				0x0a0
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP_EN				0x0a4
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP_CFG				0x0a8
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE0				0x0ac
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE0				0x0b0
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE1				0x0b4
+#define DP_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE1				0x0b8
+#define DP_V5_5NM_QSERDES_PLL_DEC_START_MODE0				0x0bc
+#define DP_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE0			0x0c0
+#define DP_V5_5NM_QSERDES_PLL_DEC_START_MODE1				0x0c4
+#define DP_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE1			0x0c8
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE0			0x0cc
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE0			0x0d0
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE0			0x0d4
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE1			0x0d8
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE1			0x0dc
+#define DP_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE1			0x0e0
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_INITVAL				0x0e4
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_EN				0x0e8
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0			0x0ec
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0			0x0f0
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1			0x0f4
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1			0x0f8
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0			0x0fc
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1			0x100
+#define DP_V5_5NM_QSERDES_PLL_VCOCAL_DEADMAN_CTRL			0x104
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_CTRL				0x108
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MAP				0x10c
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE0				0x110
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE0				0x114
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE1				0x118
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE1				0x11c
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL1				0x120
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL2				0x124
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL1				0x128
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL2				0x12c
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL1				0x130
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL2				0x134
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER1				0x138
+#define DP_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER2				0x13c
+#define DP_V5_5NM_QSERDES_PLL_CMN_STATUS				0x140
+#define DP_V5_5NM_QSERDES_PLL_RESET_SM_STATUS				0x144
+#define DP_V5_5NM_QSERDES_PLL_RESTRIM_CODE_STATUS			0x148
+#define DP_V5_5NM_QSERDES_PLL_PLLCAL_CODE1_STATUS			0x14c
+#define DP_V5_5NM_QSERDES_PLL_PLLCAL_CODE2_STATUS			0x150
+#define DP_V5_5NM_QSERDES_PLL_CLK_SELECT				0x154
+#define DP_V5_5NM_QSERDES_PLL_HSCLK_SEL					0x158
+#define DP_V5_5NM_QSERDES_PLL_HSCLK_HS_SWITCH_SEL			0x15c
+#define DP_V5_5NM_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS			0x160
+#define DP_V5_5NM_QSERDES_PLL_PLL_ANALOG				0x164
+#define DP_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE0				0x168
+#define DP_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE1				0x16c
+#define DP_V5_5NM_QSERDES_PLL_SW_RESET					0x170
+#define DP_V5_5NM_QSERDES_PLL_CORE_CLK_EN				0x174
+#define DP_V5_5NM_QSERDES_PLL_C_READY_STATUS				0x178
+#define DP_V5_5NM_QSERDES_PLL_CMN_CONFIG				0x17c
+#define DP_V5_5NM_QSERDES_PLL_CMN_RATE_OVERRIDE				0x180
+#define DP_V5_5NM_QSERDES_PLL_SVS_MODE_CLK_SEL				0x184
+#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS0				0x188
+#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS1				0x18c
+#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS2				0x190
+#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS3				0x194
+#define DP_V5_5NM_QSERDES_PLL_DEBUG_BUS_SEL				0x198
+#define DP_V5_5NM_QSERDES_PLL_CMN_MISC1					0x19c
+#define DP_V5_5NM_QSERDES_PLL_CMN_MODE					0x1a0
+#define DP_V5_5NM_QSERDES_PLL_CMN_MODE_CONTD				0x1a4
+#define DP_V5_5NM_QSERDES_PLL_VCO_DC_LEVEL_CTRL				0x1a8
+#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0		0x1ac
+#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0		0x1b0
+#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1		0x1b4
+#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1		0x1b8
+#define DP_V5_5NM_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL			0x1bc
+#define DP_V5_5NM_QSERDES_PLL_RESERVED_1				0x1c0
+#define DP_V5_5NM_QSERDES_PLL_MODE_OPERATION_STATUS			0x1c4
+
+/* Module: DP_DP_DP_PHY */
+#define DP_V5_5NM_DP_PHY_REVISION_ID0					0x000
+#define DP_V5_5NM_DP_PHY_REVISION_ID1					0x004
+#define DP_V5_5NM_DP_PHY_REVISION_ID2					0x008
+#define DP_V5_5NM_DP_PHY_REVISION_ID3					0x00c
+#define DP_V5_5NM_DP_PHY_CFG						0x010
+#define DP_V5_5NM_DP_PHY_CFG_1						0x014
+#define DP_V5_5NM_DP_PHY_PD_CTL						0x018
+#define DP_V5_5NM_DP_PHY_MODE						0x01c
+#define DP_V5_5NM_DP_PHY_AUX_CFG0					0x020
+#define DP_V5_5NM_DP_PHY_AUX_CFG1					0x024
+#define DP_V5_5NM_DP_PHY_AUX_CFG2					0x028
+#define DP_V5_5NM_DP_PHY_AUX_CFG3					0x02c
+#define DP_V5_5NM_DP_PHY_AUX_CFG4					0x030
+#define DP_V5_5NM_DP_PHY_AUX_CFG5					0x034
+#define DP_V5_5NM_DP_PHY_AUX_CFG6					0x038
+#define DP_V5_5NM_DP_PHY_AUX_CFG7					0x03c
+#define DP_V5_5NM_DP_PHY_AUX_CFG8					0x040
+#define DP_V5_5NM_DP_PHY_AUX_CFG9					0x044
+#define DP_V5_5NM_DP_PHY_AUX_CFG10					0x048
+#define DP_V5_5NM_DP_PHY_AUX_CFG11					0x04c
+#define DP_V5_5NM_DP_PHY_AUX_CFG12					0x050
+#define DP_V5_5NM_DP_PHY_AUX_INTERRUPT_MASK				0x054
+#define DP_V5_5NM_DP_PHY_AUX_INTERRUPT_CLEAR				0x058
+#define DP_V5_5NM_DP_PHY_AUX_BIST_CFG					0x05c
+#define DP_V5_5NM_DP_PHY_AUX_BIST_PRBS_SEED				0x060
+#define DP_V5_5NM_DP_PHY_AUX_BIST_PRBS_POLY				0x064
+#define DP_V5_5NM_DP_PHY_AUX_TX_PROG_PAT_16B_LSB			0x068
+#define DP_V5_5NM_DP_PHY_AUX_TX_PROG_PAT_16B_MSB			0x06c
+#define DP_V5_5NM_DP_PHY_VCO_DIV					0x070
+#define DP_V5_5NM_DP_PHY_TSYNC_OVRD					0x074
+#define DP_V5_5NM_DP_PHY_TX0_TX1_LANE_CTL				0x078
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG0				0x07c
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG1				0x080
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG2				0x084
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_CFG3				0x088
+#define DP_V5_5NM_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0			0x08c
+#define DP_V5_5NM_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1			0x090
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_PATTERN0				0x094
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_PATTERN1				0x098
+#define DP_V5_5NM_DP_PHY_TX2_TX3_LANE_CTL				0x09c
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG0				0x0a0
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG1				0x0a4
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG2				0x0a8
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_CFG3				0x0ac
+#define DP_V5_5NM_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0			0x0b0
+#define DP_V5_5NM_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1			0x0b4
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_PATTERN0				0x0b8
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_PATTERN1				0x0bc
+#define DP_V5_5NM_DP_PHY_MISR_CTRL					0x0c0
+#define DP_V5_5NM_DP_PHY_DEBUG_BUS_SEL					0x0c4
+#define DP_V5_5NM_DP_PHY_SPARE0						0x0c8
+#define DP_V5_5NM_DP_PHY_SPARE1						0x0cc
+#define DP_V5_5NM_DP_PHY_SPARE2						0x0d0
+#define DP_V5_5NM_DP_PHY_SPARE3						0x0d4
+#define DP_V5_5NM_DP_PHY_AUX_INTERRUPT_STATUS				0x0d8
+#define DP_V5_5NM_DP_PHY_STATUS						0x0dc
+#define DP_V5_5NM_DP_PHY_AUX_BIST_STATUS0				0x0e0
+#define DP_V5_5NM_DP_PHY_AUX_BIST_STATUS1				0x0e4
+#define DP_V5_5NM_DP_PHY_AUX_BIST_STATUS2				0x0e8
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_STATUS0				0x0ec
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_STATUS1				0x0f0
+#define DP_V5_5NM_DP_PHY_TX0_TX1_BIST_STATUS2				0x0f4
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_STATUS0				0x0f8
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_STATUS1				0x0fc
+#define DP_V5_5NM_DP_PHY_TX2_TX3_BIST_STATUS2				0x100
+#define DP_V5_5NM_DP_PHY_MISR_STATUS					0x104
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS000				0x108
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS001				0x10c
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS010				0x110
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS011				0x114
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS100				0x118
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS101				0x11c
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS110				0x120
+#define DP_V5_5NM_DP_PHY_TX0_MISR_STATUS111				0x124
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS000				0x128
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS001				0x12c
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS010				0x130
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS011				0x134
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS100				0x138
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS101				0x13c
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS110				0x140
+#define DP_V5_5NM_DP_PHY_TX1_MISR_STATUS111				0x144
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS000				0x148
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS001				0x14c
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS010				0x150
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS011				0x154
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS100				0x158
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS101				0x15c
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS110				0x160
+#define DP_V5_5NM_DP_PHY_TX2_MISR_STATUS111				0x164
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS000				0x168
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS001				0x16c
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS010				0x170
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS011				0x174
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS100				0x178
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS101				0x17c
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS110				0x180
+#define DP_V5_5NM_DP_PHY_TX3_MISR_STATUS111				0x184
+#define DP_V5_5NM_DP_PHY_DEBUG_BUS0					0x188
+#define DP_V5_5NM_DP_PHY_DEBUG_BUS1					0x18c
+#define DP_V5_5NM_DP_PHY_DEBUG_BUS2					0x190
+#define DP_V5_5NM_DP_PHY_DEBUG_BUS3					0x194
+
+/* Module: USB4_QSERDES_PLL_USB4_QSERDES_PLL_USB4_USB3_DP_QMP_PLL_20G */
+#define USB4_V5_5NM_QSERDES_PLL_ATB_SEL1				0x000
+#define USB4_V5_5NM_QSERDES_PLL_ATB_SEL2				0x004
+#define USB4_V5_5NM_QSERDES_PLL_FREQ_UPDATE				0x008
+#define USB4_V5_5NM_QSERDES_PLL_BG_TIMER				0x00c
+#define USB4_V5_5NM_QSERDES_PLL_SSC_EN_CENTER				0x010
+#define USB4_V5_5NM_QSERDES_PLL_SSC_ADJ_PER1				0x014
+#define USB4_V5_5NM_QSERDES_PLL_SSC_ADJ_PER2				0x018
+#define USB4_V5_5NM_QSERDES_PLL_SSC_PER1				0x01c
+#define USB4_V5_5NM_QSERDES_PLL_SSC_PER2				0x020
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE0			0x024
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE0			0x028
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE0			0x02c
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE1_MODE1			0x030
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE2_MODE1			0x034
+#define USB4_V5_5NM_QSERDES_PLL_SSC_STEP_SIZE3_MODE1			0x038
+#define USB4_V5_5NM_QSERDES_PLL_POST_DIV				0x03c
+#define USB4_V5_5NM_QSERDES_PLL_POST_DIV_MUX				0x040
+#define USB4_V5_5NM_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN			0x044
+#define USB4_V5_5NM_QSERDES_PLL_CLK_ENABLE1				0x048
+#define USB4_V5_5NM_QSERDES_PLL_SYS_CLK_CTRL				0x04c
+#define USB4_V5_5NM_QSERDES_PLL_SYSCLK_BUF_ENABLE			0x050
+#define USB4_V5_5NM_QSERDES_PLL_PLL_EN					0x054
+#define USB4_V5_5NM_QSERDES_PLL_PLL_IVCO				0x058
+#define USB4_V5_5NM_QSERDES_PLL_CMN_IETRIM				0x05c
+#define USB4_V5_5NM_QSERDES_PLL_CMN_IPTRIM				0x060
+#define USB4_V5_5NM_QSERDES_PLL_EP_CLOCK_DETECT_CTRL			0x064
+#define USB4_V5_5NM_QSERDES_PLL_SYSCLK_DET_COMP_STATUS			0x068
+#define USB4_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE0			0x06c
+#define USB4_V5_5NM_QSERDES_PLL_CLK_EP_DIV_MODE1			0x070
+#define USB4_V5_5NM_QSERDES_PLL_CP_CTRL_MODE0				0x074
+#define USB4_V5_5NM_QSERDES_PLL_CP_CTRL_MODE1				0x078
+#define USB4_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE0				0x07c
+#define USB4_V5_5NM_QSERDES_PLL_PLL_RCTRL_MODE1				0x080
+#define USB4_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE0				0x084
+#define USB4_V5_5NM_QSERDES_PLL_PLL_CCTRL_MODE1				0x088
+#define USB4_V5_5NM_QSERDES_PLL_PLL_CNTRL				0x08c
+#define USB4_V5_5NM_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM			0x090
+#define USB4_V5_5NM_QSERDES_PLL_SYSCLK_EN_SEL				0x094
+#define USB4_V5_5NM_QSERDES_PLL_CML_SYSCLK_SEL				0x098
+#define USB4_V5_5NM_QSERDES_PLL_RESETSM_CNTRL				0x09c
+#define USB4_V5_5NM_QSERDES_PLL_RESETSM_CNTRL2				0x0a0
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP_EN				0x0a4
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP_CFG				0x0a8
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE0				0x0ac
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE0				0x0b0
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP1_MODE1				0x0b4
+#define USB4_V5_5NM_QSERDES_PLL_LOCK_CMP2_MODE1				0x0b8
+#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MODE0				0x0bc
+#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE0			0x0c0
+#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MODE1				0x0c4
+#define USB4_V5_5NM_QSERDES_PLL_DEC_START_MSB_MODE1			0x0c8
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE0			0x0cc
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE0			0x0d0
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE0			0x0d4
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START1_MODE1			0x0d8
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START2_MODE1			0x0dc
+#define USB4_V5_5NM_QSERDES_PLL_DIV_FRAC_START3_MODE1			0x0e0
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_INITVAL			0x0e4
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_EN				0x0e8
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0			0x0ec
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0			0x0f0
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1			0x0f4
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1			0x0f8
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0			0x0fc
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1			0x100
+#define USB4_V5_5NM_QSERDES_PLL_VCOCAL_DEADMAN_CTRL			0x104
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_CTRL				0x108
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MAP				0x10c
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE0				0x110
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE0				0x114
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE1_MODE1				0x118
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE2_MODE1				0x11c
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL1			0x120
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_INITVAL2			0x124
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL1			0x128
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MINVAL2			0x12c
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL1			0x130
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_MAXVAL2			0x134
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER1				0x138
+#define USB4_V5_5NM_QSERDES_PLL_VCO_TUNE_TIMER2				0x13c
+#define USB4_V5_5NM_QSERDES_PLL_CMN_STATUS				0x140
+#define USB4_V5_5NM_QSERDES_PLL_RESET_SM_STATUS				0x144
+#define USB4_V5_5NM_QSERDES_PLL_RESTRIM_CODE_STATUS			0x148
+#define USB4_V5_5NM_QSERDES_PLL_PLLCAL_CODE1_STATUS			0x14c
+#define USB4_V5_5NM_QSERDES_PLL_PLLCAL_CODE2_STATUS			0x150
+#define USB4_V5_5NM_QSERDES_PLL_CLK_SELECT				0x154
+#define USB4_V5_5NM_QSERDES_PLL_HSCLK_SEL				0x158
+#define USB4_V5_5NM_QSERDES_PLL_HSCLK_HS_SWITCH_SEL			0x15c
+#define USB4_V5_5NM_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS		0x160
+#define USB4_V5_5NM_QSERDES_PLL_PLL_ANALOG				0x164
+#define USB4_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE0			0x168
+#define USB4_V5_5NM_QSERDES_PLL_CORECLK_DIV_MODE1			0x16c
+#define USB4_V5_5NM_QSERDES_PLL_SW_RESET				0x170
+#define USB4_V5_5NM_QSERDES_PLL_CORE_CLK_EN				0x174
+#define USB4_V5_5NM_QSERDES_PLL_C_READY_STATUS				0x178
+#define USB4_V5_5NM_QSERDES_PLL_CMN_CONFIG				0x17c
+#define USB4_V5_5NM_QSERDES_PLL_CMN_RATE_OVERRIDE			0x180
+#define USB4_V5_5NM_QSERDES_PLL_SVS_MODE_CLK_SEL			0x184
+#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS0				0x188
+#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS1				0x18c
+#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS2				0x190
+#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS3				0x194
+#define USB4_V5_5NM_QSERDES_PLL_DEBUG_BUS_SEL				0x198
+#define USB4_V5_5NM_QSERDES_PLL_CMN_MISC1				0x19c
+#define USB4_V5_5NM_QSERDES_PLL_CMN_MODE				0x1a0
+#define USB4_V5_5NM_QSERDES_PLL_CMN_MODE_CONTD				0x1a4
+#define USB4_V5_5NM_QSERDES_PLL_VCO_DC_LEVEL_CTRL			0x1a8
+#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0		0x1ac
+#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0		0x1b0
+#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1		0x1b4
+#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1		0x1b8
+#define USB4_V5_5NM_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL			0x1bc
+#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_CTRL_1			0x1c0
+#define USB4_V5_5NM_QSERDES_PLL_MODE_OPERATION_STATUS			0x1c4
+#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_1			0x1c8
+#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_2			0x1cc
+#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_3			0x1d0
+#define USB4_V5_5NM_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_4			0x1d4
+#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC				0x1d8
+#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_2			0x1dc
+#define USB4_V5_5NM_QSERDES_PLL_ADDITIONAL_MISC_3			0x1e0
+
+/* Module: USB4_PCS_L0_USB4_PCS_L0_USB4_PCS_LANE */
+#define USB4_V5_5NM_PCS_L0_PCS_STATUS1					0x00
+#define USB4_V5_5NM_PCS_L0_PCS_STATUS2					0x04
+#define USB4_V5_5NM_PCS_L0_PCS_STATUS3					0x08
+#define USB4_V5_5NM_PCS_L0_BIST_CHK_ERR_CNT_L_STATUS			0x0c
+#define USB4_V5_5NM_PCS_L0_BIST_CHK_ERR_CNT_H_STATUS			0x10
+#define USB4_V5_5NM_PCS_L0_BIST_CHK_STATUS				0x14
+#define USB4_V5_5NM_PCS_L0_INSIG_SW_CTRL1				0x18
+#define USB4_V5_5NM_PCS_L0_INSIG_SW_CTRL2				0x1c
+#define USB4_V5_5NM_PCS_L0_INSIG_MX_CTRL1				0x20
+#define USB4_V5_5NM_PCS_L0_INSIG_MX_CTRL2				0x24
+#define USB4_V5_5NM_PCS_L0_OUTSIG_SW_CTRL1				0x28
+#define USB4_V5_5NM_PCS_L0_OUTSIG_SW_CTRL2				0x2c
+#define USB4_V5_5NM_PCS_L0_OUTSIG_MX_CTRL1				0x30
+#define USB4_V5_5NM_PCS_L0_OUTSIG_MX_CTRL2				0x34
+#define USB4_V5_5NM_PCS_L0_PRESET_OVERRIDE_CONFIG			0x38
+#define USB4_V5_5NM_PCS_L0_TEST_CONTROL1				0x3c
+#define USB4_V5_5NM_PCS_L0_TEST_CONTROL2				0x40
+#define USB4_V5_5NM_PCS_L0_TEST_CONTROL3				0x44
+#define USB4_V5_5NM_PCS_L0_BIST_CTRL					0x48
+#define USB4_V5_5NM_PCS_L0_PRBS_SEED0					0x4c
+#define USB4_V5_5NM_PCS_L0_PRBS_SEED1					0x50
+#define USB4_V5_5NM_PCS_L0_LANE_OFF_CONFIG				0x54
+#define USB4_V5_5NM_PCS_L0_RXEQ_STATUS1					0x58
+#define USB4_V5_5NM_PCS_L0_RXEQ_STATUS2					0x5c
+#define USB4_V5_5NM_PCS_L0_RX_MARGINING_CTRL1				0x60
+#define USB4_V5_5NM_PCS_L0_RX_MARGINING_STATUS1				0x64
+#define USB4_V5_5NM_PCS_L0_RX_MARGINING_STATUS2				0x68
+
+/* Module: USB4_PCS_L1_USB4_PCS_L1_USB4_PCS_LANE */
+#define USB4_V5_5NM_PCS_L1_PCS_STATUS1					0x00
+#define USB4_V5_5NM_PCS_L1_PCS_STATUS2					0x04
+#define USB4_V5_5NM_PCS_L1_PCS_STATUS3					0x08
+#define USB4_V5_5NM_PCS_L1_BIST_CHK_ERR_CNT_L_STATUS			0x0c
+#define USB4_V5_5NM_PCS_L1_BIST_CHK_ERR_CNT_H_STATUS			0x10
+#define USB4_V5_5NM_PCS_L1_BIST_CHK_STATUS				0x14
+#define USB4_V5_5NM_PCS_L1_INSIG_SW_CTRL1				0x18
+#define USB4_V5_5NM_PCS_L1_INSIG_SW_CTRL2				0x1c
+#define USB4_V5_5NM_PCS_L1_INSIG_MX_CTRL1				0x20
+#define USB4_V5_5NM_PCS_L1_INSIG_MX_CTRL2				0x24
+#define USB4_V5_5NM_PCS_L1_OUTSIG_SW_CTRL1				0x28
+#define USB4_V5_5NM_PCS_L1_OUTSIG_SW_CTRL2				0x2c
+#define USB4_V5_5NM_PCS_L1_OUTSIG_MX_CTRL1				0x30
+#define USB4_V5_5NM_PCS_L1_OUTSIG_MX_CTRL2				0x34
+#define USB4_V5_5NM_PCS_L1_PRESET_OVERRIDE_CONFIG			0x38
+#define USB4_V5_5NM_PCS_L1_TEST_CONTROL1				0x3c
+#define USB4_V5_5NM_PCS_L1_TEST_CONTROL2				0x40
+#define USB4_V5_5NM_PCS_L1_TEST_CONTROL3				0x44
+#define USB4_V5_5NM_PCS_L1_BIST_CTRL					0x48
+#define USB4_V5_5NM_PCS_L1_PRBS_SEED0					0x4c
+#define USB4_V5_5NM_PCS_L1_PRBS_SEED1					0x50
+#define USB4_V5_5NM_PCS_L1_LANE_OFF_CONFIG				0x54
+#define USB4_V5_5NM_PCS_L1_RXEQ_STATUS1					0x58
+#define USB4_V5_5NM_PCS_L1_RXEQ_STATUS2					0x5c
+#define USB4_V5_5NM_PCS_L1_RX_MARGINING_CTRL1				0x60
+#define USB4_V5_5NM_PCS_L1_RX_MARGINING_STATUS1				0x64
+#define USB4_V5_5NM_PCS_L1_RX_MARGINING_STATUS2				0x68
+
+/* Module: USB4_PCS_USB4_PCS_USB4_PCS */
+#define USB4_V5_5NM_PCS_SW_RESET					0x000
+#define USB4_V5_5NM_PCS_REVISION_ID0					0x004
+#define USB4_V5_5NM_PCS_REVISION_ID1					0x008
+#define USB4_V5_5NM_PCS_REVISION_ID2					0x00c
+#define USB4_V5_5NM_PCS_REVISION_ID3					0x010
+#define USB4_V5_5NM_PCS_PCS_STATUS1					0x014
+#define USB4_V5_5NM_PCS_PCS_STATUS2					0x018
+#define USB4_V5_5NM_PCS_PCS_STATUS3					0x01c
+#define USB4_V5_5NM_PCS_PCS_STATUS4					0x020
+#define USB4_V5_5NM_PCS_PCS_STATUS5					0x024
+#define USB4_V5_5NM_PCS_PCS_STATUS6					0x028
+#define USB4_V5_5NM_PCS_PCS_STATUS7					0x02c
+#define USB4_V5_5NM_PCS_DEBUG_BUS_0_STATUS				0x030
+#define USB4_V5_5NM_PCS_DEBUG_BUS_1_STATUS				0x034
+#define USB4_V5_5NM_PCS_DEBUG_BUS_2_STATUS				0x038
+#define USB4_V5_5NM_PCS_DEBUG_BUS_3_STATUS				0x03c
+#define USB4_V5_5NM_PCS_POWER_DOWN_CONTROL				0x040
+#define USB4_V5_5NM_PCS_START_CONTROL					0x044
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL1					0x048
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL2					0x04c
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL3					0x050
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL4					0x054
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL5					0x058
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL6					0x05c
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL7					0x060
+#define USB4_V5_5NM_PCS_INSIG_SW_CTRL8					0x064
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL1					0x068
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL2					0x06c
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL3					0x070
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL4					0x074
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL5					0x078
+#define USB4_V5_5NM_PCS_INSIG_MX_CTRL8					0x07c
+#define USB4_V5_5NM_PCS_OUTSIG_SW_CTRL1					0x080
+#define USB4_V5_5NM_PCS_OUTSIG_MX_CTRL1					0x084
+#define USB4_V5_5NM_PCS_OUTSIG_SW_CTRL2					0x088
+#define USB4_V5_5NM_PCS_OUTSIG_MX_CTRL2					0x08c
+#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG1				0x090
+#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG2				0x094
+#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG3				0x098
+#define USB4_V5_5NM_PCS_POWER_STATE_CONFIG4				0x09c
+#define USB4_V5_5NM_PCS_FLL_CNTRL1					0x0a0
+#define USB4_V5_5NM_PCS_FLL_CNTRL2					0x0a4
+#define USB4_V5_5NM_PCS_FLL_CNT_VAL_L					0x0a8
+#define USB4_V5_5NM_PCS_FLL_CNT_VAL_H_TOL				0x0ac
+#define USB4_V5_5NM_PCS_FLL_MAN_CODE					0x0b0
+#define USB4_V5_5NM_PCS_TEST_CONTROL1					0x0b4
+#define USB4_V5_5NM_PCS_TEST_CONTROL2					0x0b8
+#define USB4_V5_5NM_PCS_TEST_CONTROL3					0x0bc
+#define USB4_V5_5NM_PCS_TEST_CONTROL4					0x0c0
+#define USB4_V5_5NM_PCS_TEST_CONTROL5					0x0c4
+#define USB4_V5_5NM_PCS_TEST_CONTROL6					0x0c8
+#define USB4_V5_5NM_PCS_TEST_CONTROL7					0x0cc
+#define USB4_V5_5NM_PCS_LOCK_DETECT_CONFIG1				0x0d0
+#define USB4_V5_5NM_PCS_LOCK_DETECT_CONFIG2				0x0d4
+#define USB4_V5_5NM_PCS_REFGEN_REQ_CONFIG1				0x0d8
+#define USB4_V5_5NM_PCS_REFGEN_REQ_CONFIG2				0x0dc
+#define USB4_V5_5NM_PCS_REFGEN_REQ_CONFIG3				0x0e0
+#define USB4_V5_5NM_PCS_BIST_CTRL					0x0e4
+#define USB4_V5_5NM_PCS_BIST_CONFIG1					0x0e8
+#define USB4_V5_5NM_PCS_BIST_CONFIG2					0x0ec
+#define USB4_V5_5NM_PCS_BIST_CONFIG3					0x0f0
+#define USB4_V5_5NM_PCS_TXMGN_CONFIG					0x0f4
+#define USB4_V5_5NM_PCS_G3_TXMGN_MAIN					0x0f8
+#define USB4_V5_5NM_PCS_G3_TXMGN_MAIN_RS				0x0fc
+#define USB4_V5_5NM_PCS_G3_PRE_GAIN					0x100
+#define USB4_V5_5NM_PCS_G3_POST_GAIN					0x104
+#define USB4_V5_5NM_PCS_G3_PRE_POST_OFFSET				0x108
+#define USB4_V5_5NM_PCS_G3_PRE_GAIN_RS					0x10c
+#define USB4_V5_5NM_PCS_G3_POST_GAIN_RS					0x110
+#define USB4_V5_5NM_PCS_G3_PRE_POST_OFFSET_RS				0x114
+#define USB4_V5_5NM_PCS_G2_TXMGN_MAIN					0x118
+#define USB4_V5_5NM_PCS_G2_TXMGN_MAIN_RS				0x11c
+#define USB4_V5_5NM_PCS_G2_PRE_GAIN					0x120
+#define USB4_V5_5NM_PCS_G2_POST_GAIN					0x124
+#define USB4_V5_5NM_PCS_G2_PRE_POST_OFFSET				0x128
+#define USB4_V5_5NM_PCS_G2_PRE_GAIN_RS					0x12c
+#define USB4_V5_5NM_PCS_G2_POST_GAIN_RS					0x130
+#define USB4_V5_5NM_PCS_G2_PRE_POST_OFFSET_RS				0x134
+#define USB4_V5_5NM_PCS_TXCOEFF_CONFIG					0x138
+#define USB4_V5_5NM_PCS_PRESET_P0_P1_PRE				0x13c
+#define USB4_V5_5NM_PCS_PRESET_P2_P3_PRE				0x140
+#define USB4_V5_5NM_PCS_PRESET_P4_P5_PRE				0x144
+#define USB4_V5_5NM_PCS_PRESET_P6_P7_PRE				0x148
+#define USB4_V5_5NM_PCS_PRESET_P8_P9_PRE				0x14c
+#define USB4_V5_5NM_PCS_PRESET_P10_P11_PRE				0x150
+#define USB4_V5_5NM_PCS_PRESET_P12_P13_PRE				0x154
+#define USB4_V5_5NM_PCS_PRESET_P14_P15_PRE				0x158
+#define USB4_V5_5NM_PCS_PRESET_P0_P1_POST				0x15c
+#define USB4_V5_5NM_PCS_PRESET_P2_P3_POST				0x160
+#define USB4_V5_5NM_PCS_PRESET_P4_P5_POST				0x164
+#define USB4_V5_5NM_PCS_PRESET_P6_P7_POST				0x168
+#define USB4_V5_5NM_PCS_PRESET_P8_P9_POST				0x16c
+#define USB4_V5_5NM_PCS_PRESET_P10_P11_POST				0x170
+#define USB4_V5_5NM_PCS_PRESET_P12_P13_POST				0x174
+#define USB4_V5_5NM_PCS_PRESET_P14_P15_POST				0x178
+#define USB4_V5_5NM_PCS_RX_SIGDET_LVL					0x17c
+#define USB4_V5_5NM_PCS_RX_SIGDET_DTCT_CNTRL				0x180
+#define USB4_V5_5NM_PCS_RATE_SLEW_CNTRL					0x184
+#define USB4_V5_5NM_PCS_PWRUP_RESET_DLY_TIME_AUXCLK			0x188
+#define USB4_V5_5NM_PCS_C3_WAKEUP_DLY_TIME_AUXCLK_L			0x18c
+#define USB4_V5_5NM_PCS_C3_WAKEUP_DLY_TIME_AUXCLK_H			0x190
+#define USB4_V5_5NM_PCS_TSYNC_RSYNC_TIME				0x194
+#define USB4_V5_5NM_PCS_CDR_RESET_TIME					0x198
+#define USB4_V5_5NM_PCS_TSYNC_DLY_TIME					0x19c
+#define USB4_V5_5NM_PCS_ELECIDLE_DLY_SEL				0x1a0
+#define USB4_V5_5NM_PCS_CMN_ACK_OUT_SEL					0x1a4
+#define USB4_V5_5NM_PCS_PCS_TX_RX_CONFIG1				0x1a8
+#define USB4_V5_5NM_PCS_PCS_TX_RX_CONFIG2				0x1ac
+#define USB4_V5_5NM_PCS_PCS_TX_RX_CONFIG3				0x1b0
+#define USB4_V5_5NM_PCS_RX_DCC_CAL_CONFIG				0x1b4
+#define USB4_V5_5NM_PCS_EQ_CONFIG1					0x1b8
+#define USB4_V5_5NM_PCS_EQ_CONFIG2					0x1bc
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG1					0x1c0
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG2					0x1c4
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG3					0x1c8
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG4					0x1cc
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG5					0x1d0
+#define USB4_V5_5NM_PCS_G2_EQ_CONFIG6					0x1d4
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG1					0x1d8
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG2					0x1dc
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG3					0x1e0
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG4					0x1e4
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG5					0x1e8
+#define USB4_V5_5NM_PCS_G3_EQ_CONFIG6					0x1ec
+#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG1					0x1f0
+#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG2					0x1f4
+#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG3					0x1f8
+#define USB4_V5_5NM_PCS_FOM_EQ_CONFIG4					0x1fc
+#define USB4_V5_5NM_PCS_LFPS_DET_HIGH_COUNT_VAL				0x200
+#define USB4_V5_5NM_PCS_LFPS_TX_ECSTART					0x204
+#define USB4_V5_5NM_PCS_LFPS_TX_END_CNT_C3_START			0x208
+#define USB4_V5_5NM_PCS_MBUS_CONFIG1					0x20c
+#define USB4_V5_5NM_PCS_MBUS_CTRL1					0x210
+#define USB4_V5_5NM_PCS_MBUS_CTRL2					0x214
+#define USB4_V5_5NM_PCS_MBUS_CTRL3					0x218
+#define USB4_V5_5NM_PCS_MBUS_CTRL4					0x21c
+#define USB4_V5_5NM_PCS_MBUS_STATUS1					0x220
+#define USB4_V5_5NM_PCS_RX_MARGINING_CONFIG1				0x224
+#define USB4_V5_5NM_PCS_RX_MARGINING_CONFIG2				0x228
+#define USB4_V5_5NM_PCS_RX_MARGINING_CONFIG3				0x22c
+#define USB4_V5_5NM_PCS_WAKEUP_CLK_CONFIG1				0x230
+#define USB4_V5_5NM_PCS_WAKEUP_CLK_CONFIG2				0x234
+#define USB4_V5_5NM_PCS_WAKEUP_CLK_STATUS				0x238
+#define USB4_V5_5NM_PCS_TX_LATENCY_MEAS_CONFIG1				0x23c
+#define USB4_V5_5NM_PCS_TX_LATENCY_MEAS_CONFIG2				0x240
+#define USB4_V5_5NM_PCS_TX_LATENCY_STATUS				0x244
+#define USB4_V5_5NM_PCS_SIGDET_CNTRL					0x248
+
+#endif
+
