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Date: Sun, 29 May 2022 20:05:35 +0300 Message-ID: <20220529170536.10043-3-michaelsh@nvidia.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20220529170536.10043-1-michaelsh@nvidia.com> References: <20220529170536.10043-1-michaelsh@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c07a80aa-c066-4371-53da-08da41957a11 X-MS-TrafficTypeDiagnostic: CY4PR1201MB0214:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qlo0DXYl3IhlP3MzDWtm/RSZqMPVZqOiiG2muqR3MwC7pYvQreJEQ99HbZk9oMDJ6B8VbHjlgWQnU0ZnDA7HFvtlRbUpdG7iia8Fr7ZDUKc8wdpisY3dI5DlYhnW8mSiQ/P2hKSdpUg1qSA5jKeosT5Du6ujgCXseJsJFi/K948xdaG3AabnEZMIzJKPvY77v8sDgALywhhKTTbV3gTvurTcmnbXX4uHnOHHQNFwPvldIvzODWbaLL83H9nbO1oWLkOrO7DxqSKew0zojHpLqfOCD3drYXUj2lp2V0MB0J7vRH0fdTrNAYLwDC8GaeQfxLEYepZ3UytB9CoTgGnf2+JjcpMjAmDMLS11hVCvXBqGlWCjzaX+uUTh1ZkcMezuF9sFMP9OD0zdlokRPXZ52z3Ki96j7kCe5cRK7EnIKWiC8JWCR1QMJQpD8/iiYVP0pvc34QIDFA9AoueIZpKF7OYcIkiKBYYKwXZ3TzTyOXyYC10Gi8Yc5hlF2R0aISPIsCDLKgbXUJ/T8e5F7VN51o0CiscXnl7PCie5icWCQgMqNJBCNWkS1Z131MaXmfW/g42LU0qe8Y2hNErPO9Et7k4Ct3W4D72Cp3+ZpTw2gNy/3IG5+9Hkeh7sM+LbiDX/uWgY+15mDye4tVmmlgavlGYdfoGqYSs1Pgf/BwgxyYQEmm4ZY7ZOVdDM6YFsSJaE0+mgqc42qlwZdqPJsf/GhwT0BcuqIMgmzHECKSLLgum87j65OFFHe32sjr3enEauRrZ7ikhJVoJA2UQXG3g5aOgY6d6vncKXjhhmLzx/Nq9ZTK1WB9hY5RFDpVDbDBA3Ew6+L7VKHbdzUknIrB7oxg== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(316002)(2616005)(81166007)(70206006)(966005)(40460700003)(36756003)(70586007)(107886003)(356005)(336012)(186003)(426003)(36860700001)(508600001)(8936002)(83380400001)(1076003)(26005)(8676002)(4326008)(6666004)(86362001)(2876002)(47076005)(2906002)(54906003)(110136005)(5660300002)(82310400005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2022 17:05:47.8985 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c07a80aa-c066-4371-53da-08da41957a11 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0214 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Michael Shych Add basic description of emc2305 driver device tree binding. Signed-off-by: Michael Shych Reviewed-by: Vadim Pasternak --- v2->v3 Changes pointed out by Rob Herring and Guenter Roeck: - Describe separate channels of fan-controller; - Remove pwm_max property; - Fix compatible property. Changes added by Michael Shych: - Fix dt binding check warnings. v1->v2 - Fix dt binding check errors; - Add descriptions; - Add missing fields; - Change the patch subject name; - Separate pwm-min, pwm-max per PWM channel. --- .../bindings/hwmon/microchip,emc2305.yaml | 106 +++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml new file mode 100644 index 000000000000..d054ba46ae23 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/hwmon/microchip,emc2305.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip EMC2305 RPM-based PWM Fan Speed Controller + +maintainers: + - Michael Shych + +description: | + Microchip EMC2301/2/3/5 are RPM-based PWM Fan Controller. + The Fan Controller supports up to 5 independently controlled PWM fan drives. + Fan rotation speeds are reported in RPM. + + Datasheet: https://www.microchip.com/en-us/product/EMC2305 + +additionalProperties: false + +properties: + compatible: + enum: + - microchip,emc2305 + - microchip,emc2303 + - microchip,emc2302 + - microchip,emc2301 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + microchip,cooling-levels: + description: + Quantity of cooling level state. + $ref: /schemas/types.yaml#/definitions/uint8 + minimum: 0 + maximum: 255 + + microchip,pwm-separate: + description: + This flag indicates that separate PWM setting will be used + for different channels. + $ref: /schemas/types.yaml#/definitions/flag + +patternProperties: + "^channel@[0-4]$": + type: object + + additionalProperties: false + + properties: + reg: + items: + - enum: + - 0 + - 1 + - 2 + - 3 + - 4 + + pwm-min: + description: + Min pwm of emc2305 channel + $ref: /schemas/types.yaml#/definitions/uint8 + minimum: 0 + maximum: 255 + + required: + - reg + +required: + - compatible + + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + fan-controller@4d { + compatible = "microchip,emc2305"; + reg = <0x4d>; + #address-cells = <1>; + #size-cells = <0>; + microchip,pwm-separate; + microchip,cooling-levels = /bits/ 8 <10>; + + channel@0 { + reg = <0>; + pwm-min = /bits/ 8 <0>; + }; + channel@1 { + reg = <1>; + pwm-min = /bits/ 8 <0>; + }; + }; + }; +