From patchwork Fri May 27 17:09:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Gore X-Patchwork-Id: 576691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AB61C43219 for ; Fri, 27 May 2022 17:10:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354220AbiE0RKE (ORCPT ); Fri, 27 May 2022 13:10:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354218AbiE0RKD (ORCPT ); Fri, 27 May 2022 13:10:03 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3714E13FD45 for ; Fri, 27 May 2022 10:10:02 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id t28so4410293pga.6 for ; Fri, 27 May 2022 10:10:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=w5OVphJHYySmPcgLg2YXRE6j7vBIZqbYrlWSKKZOvmI=; b=ZDMTC+0lVd9HVaCIb2gLJHMWK3i0Pq/u9Hdx5FiQsxxRG3LklMqbz7jQ+0pIOfA2dt vrkJTqlxVG1xBg7PHM5Y64O77IM8WhdJnT6oFTRTVeXQ1DK0599IMQHLGRu0Js7NnxZ9 eo3D/Ai8ryY4g0o2JAcHB1TEACZZAnHfyHI4c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=w5OVphJHYySmPcgLg2YXRE6j7vBIZqbYrlWSKKZOvmI=; b=5HoSAJKGnShBz+UyMebOERn3A70fPc0FQz0N/l/hQNqwTnW8t6nulwvvIjKNl/cfst w1XtBGA24ZNbPtpa4YC6yKeHTgdiHE5twIq5RC8KtSy1Wh4y74m4Pe/v6OKOTx4hUuLm b+/shok2PAy53qd1r3+MXUjZ/dqrU3i45Go88VJkehPMqUlp5ltKd/wQa/NxS5YA9kFG X0EutvG9DbkuNX7Tip0ScAp1oj15OG0xv+u3mO0tYMhOovM6fn7kiMlwf2iF0d10Nrs1 hwKij1sNCit38rtJOOoxEFyniMiXyZPw0fhW77XQGBVr9T86V1Ip/0KUZuZ22HxDyFvK 4tmw== X-Gm-Message-State: AOAM532NaVLKFZvuuNaC2D2CvQiSm3BzvPI1pqwWhanjHnFc9VuNEWAU VDeLulwE1CKtQ2TbRDQ6IuHZVA== X-Google-Smtp-Source: ABdhPJwHky09CKv208oByphNy9MKiiaHXOOhFwFxSTepcS5nJRMQBThiiBQO/tWe6Fpv6jR3CPkTEw== X-Received: by 2002:a05:6a00:1253:b0:518:7c1f:2a17 with SMTP id u19-20020a056a00125300b005187c1f2a17mr34272432pfi.72.1653671401537; Fri, 27 May 2022 10:10:01 -0700 (PDT) Received: from linuxpc-ThinkServer-TS140.dhcp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id q5-20020a6557c5000000b003f60df4a5d5sm3786151pgr.54.2022.05.27.10.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 10:10:00 -0700 (PDT) From: Anand Gore To: Linux ARM List Cc: joel.peshkin@broadcom.com, kursad.oney@broadcom.com, samyon.furman@broadcom.com, William Zhang , dan.beygelman@broadcom.com, tomer.yacoby@broadcom.com, Broadcom Kernel List , florian.fainelli@broadcom.com, Anand Gore , Arnd Bergmann , Krzysztof Kozlowski , Olof Johansson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH 1/3] ARM: dts: add dts files for bcmbca soc 6878 Date: Fri, 27 May 2022 10:09:08 -0700 Message-Id: <20220527100904.1.I0ef47baf3d32d36f823c539c3da3735a6b3e855b@changeid> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220527170910.2461134-1-anand.gore@broadcom.com> References: <20220527170910.2461134-1-anand.gore@broadcom.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dts for ARMv7 based broadband SoC BCM6878. bcm63178.dtsi is the SoC description dts header and bcm96878.dts is a simple dts file for Broadcom BCM96878 Reference board that only enable the UART port. Signed-off-by: Anand Gore --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/bcm6878.dtsi | 109 +++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm96878.dts | 30 +++++++++ 3 files changed, 141 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/bcm6878.dtsi create mode 100644 arch/arm/boot/dts/bcm96878.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d9ac59524408..553fef458926 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -183,7 +183,8 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb dtb-$(CONFIG_ARCH_BCMBCA) += \ bcm947622.dtb \ - bcm963178.dtb + bcm963178.dtb \ + bcm96878.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi new file mode 100644 index 000000000000..167a3f78f1f4 --- /dev/null +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm6878", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x4000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/bcm96878.dts new file mode 100644 index 000000000000..8fbc175cb452 --- /dev/null +++ b/arch/arm/boot/dts/bcm96878.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6878.dtsi" + +/ { + model = "Broadcom BCM96878 Reference Board"; + compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};