From patchwork Mon May 23 06:00:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 575605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54E91C43217 for ; Mon, 23 May 2022 06:01:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234226AbiEWGBd (ORCPT ); Mon, 23 May 2022 02:01:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232412AbiEWGBO (ORCPT ); Mon, 23 May 2022 02:01:14 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41BF4CE8; Sun, 22 May 2022 23:01:10 -0700 (PDT) X-UUID: 626d9003dcda496696a24d4a0cd7adb3-20220523 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:5c32bb53-0d0c-44d1-a758-84a8a80716cb, OB:20, L OB:40,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham, ACTION:release,TS:90 X-CID-INFO: VERSION:1.1.5, REQID:5c32bb53-0d0c-44d1-a758-84a8a80716cb, OB:20, LOB :40,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:90 X-CID-META: VersionHash:2a19b09, CLOUDID:0c7b2ee3-edbf-4bd4-8a34-dfc5f7bb086d, C OID:4bfce04ef61e,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 626d9003dcda496696a24d4a0cd7adb3-20220523 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1606270458; Mon, 23 May 2022 14:00:59 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 23 May 2022 14:00:58 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 23 May 2022 14:00:58 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v8 09/19] clk: mediatek: reset: Change return type for clock reset register function Date: Mon, 23 May 2022 14:00:46 +0800 Message-ID: <20220523060056.24396-10-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220523060056.24396-1-rex-bc.chen@mediatek.com> References: <20220523060056.24396-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org To deal with error handling, we change the function return type from void to int for mtk_clk_register_rst_ctrl(). Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado --- drivers/clk/mediatek/reset.c | 15 +++++++++------ drivers/clk/mediatek/reset.h | 6 ++++-- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 89e617ea6393..b9718f0f9d16 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -110,8 +110,8 @@ static int reset_xlate(struct reset_controller_dev *rcdev, return data->desc->rst_idx_map[reset_spec->args[0]]; } -void mtk_register_reset_controller(struct device_node *np, - const struct mtk_clk_rst_desc *desc) +int mtk_register_reset_controller(struct device_node *np, + const struct mtk_clk_rst_desc *desc) { struct regmap *regmap; const struct reset_control_ops *rcops = NULL; @@ -120,7 +120,7 @@ void mtk_register_reset_controller(struct device_node *np, if (!desc) { pr_err("mtk clock reset desc is NULL\n"); - return; + return -EINVAL; } switch (desc->version) { @@ -132,18 +132,18 @@ void mtk_register_reset_controller(struct device_node *np, break; default: pr_err("Unknown reset version %d\n", desc->version); - return; + return -EINVAL; } regmap = device_node_to_regmap(np); if (IS_ERR(regmap)) { pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap); - return; + return -EINVAL; } data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) - return; + return -ENOMEM; data->desc = desc; data->regmap = regmap; @@ -163,7 +163,10 @@ void mtk_register_reset_controller(struct device_node *np, if (ret) { pr_err("could not register reset controller: %d\n", ret); kfree(data); + return ret; } + + return 0; } MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index cc847c67a2fc..260f25f27656 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -56,8 +56,10 @@ struct mtk_clk_rst_data { * mtk_register_reset_controller - Register MediaTek clock reset controller * @np: Pointer to device node. * @desc: Constant pointer to description of clock reset. + * + * Return: 0 on success and errorno otherwise. */ -void mtk_register_reset_controller(struct device_node *np, - const struct mtk_clk_rst_desc *desc); +int mtk_register_reset_controller(struct device_node *np, + const struct mtk_clk_rst_desc *desc); #endif /* __DRV_CLK_MTK_RESET_H */