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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id h2-20020a1ccc02000000b0039466988f6csm7802414wmb.31.2022.05.22.22.28.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 May 2022 22:28:17 -0700 (PDT) From: Corentin Labbe To: andrew@lunn.ch, broonie@kernel.org, calvin.johnson@oss.nxp.com, davem@davemloft.net, edumazet@google.com, hkallweit1@gmail.com, jernej.skrabec@gmail.com, krzysztof.kozlowski+dt@linaro.org, kuba@kernel.org, lgirdwood@gmail.com, linux@armlinux.org.uk, pabeni@redhat.com, robh+dt@kernel.org, samuel@sholland.org, wens@csie.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, netdev@vger.kernel.org, =?utf-8?q?Ond=C5=99ej_Jirman?= , Corentin Labbe Subject: [PATCH v3 3/3] arm64: dts: allwinner: orange-pi-3: Enable ethernet Date: Mon, 23 May 2022 05:28:07 +0000 Message-Id: <20220523052807.4044800-4-clabbe@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220523052807.4044800-1-clabbe@baylibre.com> References: <20220523052807.4044800-1-clabbe@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: OndÅ™ej Jirman Orange Pi 3 has two regulators that power the Realtek RTL8211E PHY. According to the datasheet, both regulators need to be enabled at the same time, or that "phy-io" should be enabled slightly earlier than "phy" regulator. RTL8211E/RTL8211EG datasheet says: Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power later than 3.3V power may lead to errors. The timing is set in DT via startup-delay-us. Signed-off-by: Ondrej Jirman Signed-off-by: Corentin Labbe --- .../dts/allwinner/sun50i-h6-orangepi-3.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index c45d7b7fb39a..2760a0bf76d5 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -13,6 +13,7 @@ / { compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -55,6 +56,15 @@ led-1 { }; }; + reg_gmac_2v5: gmac-2v5 { + compatible = "regulator-fixed"; + regulator-name = "gmac-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; + reg_vcc5v: vcc5v { /* board wide 5V supply directly from the DC jack */ compatible = "regulator-fixed"; @@ -113,6 +123,33 @@ &ehci3 { status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + /* + * The board uses 2.5V RGMII signalling. Power sequence to enable + * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails + * at the same time and to wait 100ms. The driver enables phy-io + * first. Delay is achieved with enable-ramp-delay on reg_aldo2. + */ + phy-io-supply = <®_gmac_2v5>; + ephy-supply = <®_aldo2>; + + reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ + reset-assert-us = <15000>; + reset-deassert-us = <40000>; + }; +}; + &gpu { mali-supply = <®_dcdcc>; status = "okay"; @@ -211,6 +248,7 @@ reg_aldo2: aldo2 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc33-audio-tv-ephy-mac"; + regulator-enable-ramp-delay = <100000>; }; /* ALDO3 is shorted to CLDO1 */