From patchwork Fri May 20 18:31:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 575133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56743C433F5 for ; Fri, 20 May 2022 18:32:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352839AbiETScC (ORCPT ); Fri, 20 May 2022 14:32:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352730AbiETSb5 (ORCPT ); Fri, 20 May 2022 14:31:57 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B3613BBD7 for ; Fri, 20 May 2022 11:31:28 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id bu29so15838318lfb.0 for ; Fri, 20 May 2022 11:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HYUuQ4fR4SBZdSuM6IAnUnoggotKrAQZZIhO70s2q7Y=; b=X4oIh/DT61PtzHnpKmzPraEthERRUoDiBARoyBkbYkzGlvqpPpDy+F3bl/qWEKGNo9 JjHVe3kxX9YQC0w40D/IzfH1CvaV3hyidNGxlPd2F7EPOcE3zSr3mQWHV10M4nTPuYNb mqB2s78/8THZqtl8dn3v9/swEqTFGbu4y4m22wPB2L7QHrGbWWd6LhuXbSN8915T5dUb PNbVGcT5dx3edrQgPhc6AgoXAj9NyPBG+9FHtep2v5jUpGXGQsMLIoMKxG1RjMAJMKI6 OLn6tM/2p15Ileo9y/Uc2ZTfo/NU8+x8sH5LbY8mtx8MRdtFcJOfRgKSLF2KdagRB2DI ePIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HYUuQ4fR4SBZdSuM6IAnUnoggotKrAQZZIhO70s2q7Y=; b=XNl7MzxovhfKQTvJkqQGiVxF09CvcVthc68It1ro4elL4pK+Zvz1Jhe7HYQER0rcBp uxCLsU+ykWwW3NTL93Geg9/ZIKlSfKQpsPymfvLqNL7SlHYDTq7bvu5tKbzl8KCQK3mo sqQ18saIcegMEToBLaxQ0ar3eWP0epyoFqZgWaa14IAvkGJvL3CNQJOWkwtnT48cBNET MWCOlgy2JAGALsJK0peJDUButvQP7vaYGmX1yNK5aHLJJfCv8nD7kLBmIV7Qc7vk/3Ly x26JzOI6SjA3cIa0xTNy9twm4GxJzzgwu3vl7yHJ5bPWI3ytzGx/SB3G/Cs/ClcnJxxn GOsg== X-Gm-Message-State: AOAM530ck/qemoFlsEj5qOYtv9ObnnVB9LMl7NR44HNmt1ARwFMMvLIM K9bTwwHypNdz8FQlYJcknWEQsg== X-Google-Smtp-Source: ABdhPJzyVbKMJ57kOGL6RNEQwGiVIM9HKUDkUtE2x/DdTnx8ibeKSJSQhlA3lBM/180aZs3zNapMpA== X-Received: by 2002:a19:7115:0:b0:473:f2a7:661 with SMTP id m21-20020a197115000000b00473f2a70661mr7250781lfc.586.1653071486030; Fri, 20 May 2022 11:31:26 -0700 (PDT) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id t22-20020a2e9556000000b0024f3d1daef4sm392951ljh.124.2022.05.20.11.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 11:31:25 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Johan Hovold , Krzysztof Kozlowski Subject: [PATCH v11 5/7] dt-bindings: PCI: qcom: Support additional MSI interrupts Date: Fri, 20 May 2022 21:31:12 +0300 Message-Id: <20220520183114.1356599-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520183114.1356599-1-dmitry.baryshkov@linaro.org> References: <20220520183114.1356599-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Qualcomm platforms each group of 32 MSI vectors is routed to the separate GIC interrupt. Document mapping of additional interrupts. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.yaml | 53 +++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 0b69b12b849e..fe8f9a62a665 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -43,11 +43,12 @@ properties: maxItems: 5 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 8 interrupt-names: - items: - - const: msi + minItems: 1 + maxItems: 8 # Common definitions for clocks, clock-names and reset. # Platform constraints are described later. @@ -623,6 +624,52 @@ allOf: - resets - reset-names + # On newer chipsets support either 1 or 8 msi interrupts + # On older chipsets it's always 1 msi interrupt + - if: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + oneOf: + - properties: + interrupts: + maxItems: 1 + interrupt-names: + maxItems: 1 + items: + - const: msi + - properties: + interrupts: + minItems: 8 + interrupt-names: + minItems: 8 + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: msi + unevaluatedProperties: false examples: