From patchwork Fri May 13 17:16:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 572663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D832AC433EF for ; Fri, 13 May 2022 17:16:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382852AbiEMRQu (ORCPT ); Fri, 13 May 2022 13:16:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382835AbiEMRQk (ORCPT ); Fri, 13 May 2022 13:16:40 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E7CA3122B; Fri, 13 May 2022 10:16:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 9A82C1F463B2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652462187; bh=xHDizGEAS5CEUxEZaxa3laKX/jFEH45gEkIh0l+Zvvk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=norOKTi32tuUwqGq38L3Hc4rQbrVKvPwvxJ3Nj/2aEw5sd8upvUxOAaR+YWmKI9F3 nDQr2MUsdwQ1ksgr94q5xytYzl83x9hX2EpZeGZWdTbJZyqTBcdmqPpIqEJVYecyfn inVEIsFvYifnB9JyLEl+KF0FmKDrDInSYiycOwl8lllrx23et5EUFJCry+ubx34xkf PwA3j7UpPVQo8DIeH/PxUp915eKaJfU8eVC0KKxg3+TXWAKl7Hu++qOmYHeAGuuf7g xwRRpCFR6sH2uuC12t92Uh88FOSOmcA8QZFp1MhDJTiRFggczrDajx03dIagDPp7J0 zLXrReUdCMDeA== From: AngeloGioacchino Del Regno To: robh+dt@kernel.org Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, kernel@collabora.com, AngeloGioacchino Del Regno Subject: [PATCH 5/7] arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs Date: Fri, 13 May 2022 19:16:15 +0200 Message-Id: <20220513171617.504430-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> References: <20220513171617.504430-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the 32kHz and 26MHz oscillators as fixed clocks in devicetree to provide a good initial clock spec, since this SoC features two always on oscillators running at the aforementioned frequencies. While at it, since the UART clock is actually referring to the 26MHz oscillator, remove it and assign clk26m as "baud" clock for the UARTs. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 363fa25b4edc..b6f7681cc151 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -142,21 +142,23 @@ l2_1: l2-cache1 { }; }; - system_clk: dummy13m { + clk26m: oscillator-26m { compatible = "fixed-clock"; - clock-frequency = <13000000>; #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; }; - rtc_clk: dummy32k { + clk32k: oscillator-32k { compatible = "fixed-clock"; - clock-frequency = <32000>; #clock-cells = <0>; + clock-frequency = <32000>; + clock-output-names = "clk32k"; }; - uart_clk: dummy26m { + system_clk: dummy13m { compatible = "fixed-clock"; - clock-frequency = <26000000>; + clock-frequency = <13000000>; #clock-cells = <0>; }; @@ -221,7 +223,7 @@ uart0: serial@11002000 { "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -230,7 +232,7 @@ uart1: serial@11003000 { "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -239,7 +241,7 @@ uart2: serial@11004000 { "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; @@ -248,7 +250,7 @@ uart3: serial@11005000 { "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&clk26m>; status = "disabled"; }; };