| Message ID | 20220425182249.2753690-1-robimarko@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/7] clk: qcom: ipq8074: fix NSS core PLL-s | expand |
On Fri, 6 May 2022 at 05:33, Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > On Mon 25 Apr 13:22 CDT 2022, Robert Marko wrote: > > > Like in IPQ6018 Qualcomm intentionally disables the SW_COLLAPSE on the USB > > GDSC-s in the downstream 5.4 kernel. > > > > This could potentially be better handled by utilizing the GDSC driver, but > > I am not familiar with it nor do I have datasheets. > > Could you please give it a try before we pick this up? > Look at e.g. drivers/clk/qcom/gcc-sdm845.c how usb30_prim_gdsc and > usb30_sec_gdsc are defined, the offsets in specified in .gdscr should be > the same offsets you give below. > > Then you specify an array of struct gdsc *, associating the two gdscs > you have specified to some identifier (USB30_PRIM_GDSC and > USB30_SEC_GDSC is used in sdm845) and reference this list as .gdscs and > num_gdscs in the gcc_ipq8074_desc. > > The last part is to tie the USB controllers to the two GDSCs, this is > done by simply specifying: > > power-domains = <&gcc USB30_PRIM_GDSC>; > > and USB30_SEC_GDSC, in the two USB nodes in DeviceTree. SW_COLLAPSE will > be toggled by the PM state of the USB driver, like it's done on e.g. > sdm845. Hi Bjorn, thanks for the tips, it makes more sense now. The only thing I am not sure about are the feature flags for these GDSCs, how to figure out which ones are correct as I dont have datasheets and QCA does not use GDSCs in the downstream kernel? POLL_CFG_GDSCR will cause the GDSC not to get enabled, while VOTABLE seems to work. Regards, Robert > > Regards, > Bjorn > > > > > Signed-off-by: Robert Marko <robimarko@gmail.com> > > --- > > drivers/clk/qcom/gcc-ipq8074.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c > > index 2ebd1462db78..65249a03a672 100644 > > --- a/drivers/clk/qcom/gcc-ipq8074.c > > +++ b/drivers/clk/qcom/gcc-ipq8074.c > > @@ -4806,6 +4806,11 @@ static int gcc_ipq8074_probe(struct platform_device *pdev) > > if (IS_ERR(regmap)) > > return PTR_ERR(regmap); > > > > + /* Disable SW_COLLAPSE for USB0 GDSCR */ > > + regmap_update_bits(regmap, 0x3e078, BIT(0), 0x0); > > + /* Disable SW_COLLAPSE for USB1 GDSCR */ > > + regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); > > + > > clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); > > clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, > > &nss_crypto_pll_config); > > -- > > 2.35.1 > >
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index e79c3329febd..2ebd1462db78 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -4371,6 +4371,33 @@ static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { }, }; +static const struct alpha_pll_config ubi32_pll_config = { + .l = 0x4e, + .config_ctl_val = 0x200d4aa8, + .config_ctl_hi_val = 0x3c2, + .main_output_mask = BIT(0), + .aux_output_mask = BIT(1), + .pre_div_val = 0x0, + .pre_div_mask = BIT(12), + .post_div_val = 0x0, + .post_div_mask = GENMASK(9, 8), +}; + +static const struct alpha_pll_config nss_crypto_pll_config = { + .l = 0x3e, + .alpha = 0x0, + .alpha_hi = 0x80, + .config_ctl_val = 0x4001055b, + .main_output_mask = BIT(0), + .pre_div_val = 0x0, + .pre_div_mask = GENMASK(14, 12), + .post_div_val = 0x1 << 8, + .post_div_mask = GENMASK(11, 8), + .vco_mask = GENMASK(21, 20), + .vco_val = 0x0, + .alpha_en_mask = BIT(24), +}; + static struct clk_hw *gcc_ipq8074_hws[] = { &gpll0_out_main_div2.hw, &gpll6_out_main_div2.hw, @@ -4773,7 +4800,17 @@ static const struct qcom_cc_desc gcc_ipq8074_desc = { static int gcc_ipq8074_probe(struct platform_device *pdev) { - return qcom_cc_probe(pdev, &gcc_ipq8074_desc); + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); + + return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap); } static struct platform_driver gcc_ipq8074_driver = {
Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration to work. So, obtain the regmap that is required for the Alpha PLL configuration and thus utilize the qcom_cc_really_probe() as we already have the regmap. Then utilize the Alpha PLL configs from the downstream QCA 5.4 based kernel to configure them. This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the kernel. Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Robert Marko <robimarko@gmail.com> --- drivers/clk/qcom/gcc-ipq8074.c | 39 +++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)