From patchwork Tue Apr 19 23:03:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 563474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74D9BC433F5 for ; Tue, 19 Apr 2022 23:03:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347386AbiDSXGQ (ORCPT ); Tue, 19 Apr 2022 19:06:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347369AbiDSXGQ (ORCPT ); Tue, 19 Apr 2022 19:06:16 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C3DA2611E; Tue, 19 Apr 2022 16:03:32 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 80EA022248; Wed, 20 Apr 2022 01:03:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1650409410; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pF8LG5F8NwFab7DCpCeNAFG08MwxqutfST9nL8U0DGU=; b=Q5X/L/9QQ278d/vKZfhx5R5kJ6qyUhY26zHq8B5oKJQ+J5lVc4nHIJVR8OIuY4jr4yI4tC gq/RhDPbaUcuBSzdaVGVfFw2kZL2AfY9ilGZi/qY4DJDbLsU5gd4t4GfFv8a2O+jjt+mrq wzVHEHKNJfCgSCykbvc7zXB2lCSb9J8= From: Michael Walle To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , Alexandre Belloni , Lars Povlsen Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Horatiu Vultur , Michael Walle , Rob Herring Subject: [PATCH v2 1/2] dt-bindings: pinctrl: ocelot: add reset property Date: Wed, 20 Apr 2022 01:03:23 +0200 Message-Id: <20220419230324.3221779-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220419230324.3221779-1-michael@walle.cc> References: <20220419230324.3221779-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On the LAN966x SoC the GPIO controller will be resetted together with the SGPIO and the switch core. Add a phandle to register the shared reset line. Signed-off-by: Michael Walle Acked-by: Rob Herring --- .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml index 7149a6655623..98d547c34ef3 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -42,6 +42,14 @@ properties: "#interrupt-cells": const: 2 + resets: + maxItems: 1 + + reset-names: + description: Optional shared switch reset. + items: + - const: switch + patternProperties: '-pins$': type: object