From patchwork Mon Apr 18 08:27:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 563186 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42A79C433FE for ; Mon, 18 Apr 2022 08:27:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237240AbiDRIa1 (ORCPT ); Mon, 18 Apr 2022 04:30:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229636AbiDRIa0 (ORCPT ); Mon, 18 Apr 2022 04:30:26 -0400 Received: from maillog.nuvoton.com (maillog.nuvoton.com [202.39.227.15]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A7D9A193DA; Mon, 18 Apr 2022 01:27:47 -0700 (PDT) Received: from NTHCCAS01.nuvoton.com (NTHCCAS01.nuvoton.com [10.1.8.28]) by maillog.nuvoton.com (Postfix) with ESMTP id 632761C8128E; Mon, 18 Apr 2022 16:27:46 +0800 (CST) Received: from NTHCCAS04.nuvoton.com (10.1.8.29) by NTHCCAS01.nuvoton.com (10.1.8.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2375.7; Mon, 18 Apr 2022 16:27:46 +0800 Received: from localhost.localdomain (172.19.1.47) by NTHCCAS04.nuvoton.com (10.1.12.25) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Mon, 18 Apr 2022 16:27:45 +0800 From: Jacky Huang To: , , , , CC: , , , , , , , , Jacky Huang Subject: [PATCH v3 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings Date: Mon, 18 Apr 2022 16:27:35 +0800 Message-ID: <20220418082738.11301-3-ychuang3@nuvoton.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220418082738.11301-1-ychuang3@nuvoton.com> References: <20220418082738.11301-1-ychuang3@nuvoton.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation to describe Nuvoton MA35D1 clock driver bindings. Signed-off-by: Jacky Huang --- .../bindings/clock/nuvoton,ma35d1-clk.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml new file mode 100644 index 000000000000..d0d37c5e84af --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,ma35d1-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Clock Control Module Binding + +maintainers: + - Chi-Fang Li + - Jacky Huang + +description: | + The MA35D1 clock controller generates clocks for the whole chip, + including system clocks and all peripheral clocks. + + See also: + include/dt-bindings/clock/ma35d1-clk.h + +properties: + compatible: + const: nuvoton,ma35d1-clk + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + assigned-clocks: + minItems: 5 + maxItems: 5 + + assigned-clock-rates: + minItems: 5 + maxItems: 5 + + nuvoton,clk-pll-mode: + A list of PLL operation mode corresponding to DDRPLL, APLL, EPLL, + and VPLL in sequential. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 5 + maxItems: 5 + items: + enum: [ 0, 1, 2 ] + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + + clk: clock-controller@40460200 { + compatible = "nuvoton,ma35d1-clk"; + reg = <0x0 0x40460200 0x0 0x100>; + #clock-cells = <1>; + }; +...