From patchwork Wed Apr 13 22:19:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 560949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C68CC433F5 for ; Wed, 13 Apr 2022 22:20:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236762AbiDMWWh (ORCPT ); Wed, 13 Apr 2022 18:22:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236972AbiDMWWE (ORCPT ); Wed, 13 Apr 2022 18:22:04 -0400 Received: from out5-smtp.messagingengine.com (out5-smtp.messagingengine.com [66.111.4.29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ED8322B14; Wed, 13 Apr 2022 15:19:40 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id E12FD5C0325; Wed, 13 Apr 2022 18:19:39 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Wed, 13 Apr 2022 18:19:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1649888379; x=1649974779; bh=Dm EyWFCtmS1CP/NJfSjamUUamIi9FMNiWBV0XLSX5tI=; b=mk4goxXUJrAIBWW089 dPCf4FzqENNN0V90qnVFG3Nb+06XXWnUrXuZ+EZ6KlLvmQlaXV9aLyBEheUsB0ew L5IA+VDexu9UDz6dGM6mmgxkKvzzLYGjP3cMHo+hVZIF9kC4V64sjU8qx/jOcs5L jlN3BOhlSz0a0f8q0SsMtOtEcWU+yNnikHz1LQO4RRSxkHIRCE10BA5ek86yu7kT YGh49nlDZ1paW0U8O6XzmoK5UGs8+a9UjY3n4SLqsWmX0JGaC9H0+lMli/eqGBVM cVPioWFJsFXzAiGrvp8NspW1xYpvIJB3aadgENPWLfBujOblEA6ajcicj3TfRgLF hqAA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:in-reply-to:message-id:mime-version :references:reply-to:sender:subject:subject:to:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; t= 1649888379; x=1649974779; bh=DmEyWFCtmS1CP/NJfSjamUUamIi9FMNiWBV 0XLSX5tI=; b=p2cP5wLcgSeBDjXtnvHzgbPSPk4yR/i4fCkA7ZcCtNYo63XOpfs MCD6IQpVv1+Dvi4dKKDfk+b8QKvo5zbtk2n5xvgts/v2zX/asrYoVUsHHdKl9HFe JMyLH2eL4Wed7wNTe/mHykvgiIexwOTkhsl1xC7ch91CbBfLRCmRojvmG3ULGkcE 81bnvhj5CVzIrQwrXEOlTtS2CmAek3tdrY1DYseSt/Qy+M/F9XzVk7cV+73LN0j7 LXhmz0c/y0R+OnY/q2gBsADIuhWFUhCq+nKEuOlqY/X61x3YGdggRtcCqiea/L4Y VKkfy76tni9n76SXAE+h/l2bjLPG34bnGXw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvvddrudelvddgtdelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucevlhhushhtvghrufhiiigvpedvnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 13 Apr 2022 18:19:38 -0400 (EDT) From: Samuel Holland To: =?utf-8?q?Heiko_St=C3=BCbner?= , Sandy Huang , dri-devel@lists.freedesktop.org Cc: linux-rockchip@lists.infradead.org, Alistair Francis , =?utf-8?q?Ond=C5=99ej_Jirman?= , Andreas Kemnade , Daniel Vetter , David Airlie , Geert Uytterhoeven , Samuel Holland , Krzysztof Kozlowski , Liang Chen , Maarten Lankhorst , Maxime Ripard , Michael Riesch , Nicolas Frattaroli , Peter Geis , Rob Herring , Sam Ravnborg , Thierry Reding , Thomas Zimmermann , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 09/16] drm/rockchip: ebc: Implement global refreshes Date: Wed, 13 Apr 2022 17:19:09 -0500 Message-Id: <20220413221916.50995-10-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220413221916.50995-1-samuel@sholland.org> References: <20220413221916.50995-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The global refresh mode is used to initialize and clear the screen. It is the most efficient refresh mode. It uses two pixel buffers (old and new) and a frame count. The frame count is set to the number of phases in the waveform. The hardware then looks up the combination of (old pixel value, new pixel value, frame number) in the LUT and sends the resulting polarity value to the display. Signed-off-by: Samuel Holland --- drivers/gpu/drm/rockchip/rockchip_ebc.c | 48 ++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_ebc.c b/drivers/gpu/drm/rockchip/rockchip_ebc.c index ca3173b28d1c..cb6dc567e94c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_ebc.c +++ b/drivers/gpu/drm/rockchip/rockchip_ebc.c @@ -127,6 +127,7 @@ #define EBC_NUM_LUT_REGS 0x1000 #define EBC_NUM_SUPPLIES 3 +#define EBC_REFRESH_TIMEOUT msecs_to_jiffies(3000) #define EBC_SUSPEND_DELAY_MS 2000 struct rockchip_ebc { @@ -269,8 +270,23 @@ static void rockchip_ebc_global_refresh(struct rockchip_ebc *ebc, { struct drm_device *drm = &ebc->drm; u32 gray4_size = ctx->gray4_size; + struct device *dev = drm->dev; - drm_dbg(drm, "global refresh\n"); + dma_sync_single_for_device(dev, virt_to_phys(ctx->next), + gray4_size, DMA_TO_DEVICE); + dma_sync_single_for_device(dev, virt_to_phys(ctx->prev), + gray4_size, DMA_TO_DEVICE); + + reinit_completion(&ebc->display_end); + regmap_write(ebc->regmap, EBC_CONFIG_DONE, + EBC_CONFIG_DONE_REG_CONFIG_DONE); + regmap_write(ebc->regmap, EBC_DSP_START, + ebc->dsp_start | + EBC_DSP_START_DSP_FRM_TOTAL(ebc->lut.num_phases - 1) | + EBC_DSP_START_DSP_FRM_START); + if (!wait_for_completion_timeout(&ebc->display_end, + EBC_REFRESH_TIMEOUT)) + drm_err(drm, "Refresh timed out!\n"); memcpy(ctx->prev, ctx->next, gray4_size); } @@ -289,6 +305,7 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc, enum drm_epd_waveform waveform) { struct drm_device *drm = &ebc->drm; + u32 dsp_ctrl = 0, epd_ctrl = 0; struct device *dev = drm->dev; int ret, temperature; @@ -334,11 +351,40 @@ static void rockchip_ebc_refresh(struct rockchip_ebc *ebc, ebc->lut.buf, EBC_NUM_LUT_REGS); } + regmap_write(ebc->regmap, EBC_DSP_START, + ebc->dsp_start); + + /* + * The hardware has a separate bit for each mode, with some priority + * scheme between them. For clarity, only set one bit at a time. + */ + if (global_refresh) { + dsp_ctrl |= EBC_DSP_CTRL_DSP_LUT_MODE; + } else { + epd_ctrl |= EBC_EPD_CTRL_DSP_THREE_WIN_MODE; + } + regmap_update_bits(ebc->regmap, EBC_EPD_CTRL, + EBC_EPD_CTRL_DSP_THREE_WIN_MODE, + epd_ctrl); + regmap_update_bits(ebc->regmap, EBC_DSP_CTRL, + EBC_DSP_CTRL_DSP_LUT_MODE, + dsp_ctrl); + + regmap_write(ebc->regmap, EBC_WIN_MST0, + virt_to_phys(ctx->next)); + regmap_write(ebc->regmap, EBC_WIN_MST1, + virt_to_phys(ctx->prev)); + if (global_refresh) rockchip_ebc_global_refresh(ebc, ctx); else rockchip_ebc_partial_refresh(ebc, ctx); + /* Drive the output pins low once the refresh is complete. */ + regmap_write(ebc->regmap, EBC_DSP_START, + ebc->dsp_start | + EBC_DSP_START_DSP_OUT_LOW); + pm_runtime_mark_last_busy(dev); pm_runtime_put_autosuspend(dev); }