From patchwork Fri Apr 8 14:36:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 559329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8B03C4332F for ; Fri, 8 Apr 2022 14:37:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236978AbiDHOju (ORCPT ); Fri, 8 Apr 2022 10:39:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236959AbiDHOjt (ORCPT ); Fri, 8 Apr 2022 10:39:49 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04C73888F3; Fri, 8 Apr 2022 07:37:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649428666; x=1680964666; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BVZx33NKupiZCfwz779hCCkPFx236F041juK4+XrqfM=; b=fV8G16XqBcxmxJraGSSJKWc6MManq5j6wuqJYsSt9xznRll9SUuWi60n NRS+0wfonuSMYLQimEZlghhj+Z75hqctbkIg/TwUIX7xr1QsveBjVSdL1 cJPwWFP7/ijRc0kLAwDnTIQOLJOoknGnElQywl0SFESILi/nKv9jp0U0L cCCZ4SoadqsptwvuxkiNXBs5+PRoHxTVg1Dmwk6UE9l3QqnCw/SWIKCOg uERGKhrlbGIwxoDPIPHJoXG6NQaSEt3zkpRqdSXOvyet3vQmjY0ONEwL8 xK9qOiVTPJn7q9h+HNKmn++0Y7n0e4lwZVlkppW709I+nDgDsKiPFuE+J w==; X-IronPort-AV: E=Sophos;i="5.90,245,1643698800"; d="scan'208";a="152027968" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Apr 2022 07:37:45 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Apr 2022 07:37:45 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Apr 2022 07:37:41 -0700 From: Conor Dooley To: , , , , , , , , CC: , , , , , Conor Dooley Subject: [PATCH v1 1/7] dt-bindings: clk: mpfs document msspll dri registers Date: Fri, 8 Apr 2022 14:36:41 +0000 Message-ID: <20220408143646.3693104-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220408143646.3693104-1-conor.dooley@microchip.com> References: <20220408143646.3693104-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As there are two sections of registers that are responsible for clock configuration on the PolarFire SoC: add the dynamic reconfiguration interface section to the binding & describe what each of the sections are used for. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- .../devicetree/bindings/clock/microchip,mpfs.yaml | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml index 0c15afa2214c..42919df322ab 100644 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml @@ -22,7 +22,14 @@ properties: const: microchip,mpfs-clkcfg reg: - maxItems: 1 + items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, axi, ahb and + rtc/mtimer reference clocks as well as enable and reset for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss pll clocks: maxItems: 1 @@ -51,7 +58,7 @@ examples: #size-cells = <2>; clkcfg: clock-controller@20002000 { compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&ref>; #clock-cells = <1>; };