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[109.49.33.111]) by smtp.gmail.com with ESMTPSA id az19-20020a05600c601300b0038cadf3aa69sm11622812wmb.36.2022.03.31.08.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 08:45:49 -0700 (PDT) From: Rui Miguel Silva To: Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Rui Miguel Silva Subject: [PATCH v4 1/3] dt-bindings: net: smsc,lan91c111 convert to schema Date: Thu, 31 Mar 2022 16:45:34 +0100 Message-Id: <20220331154536.1544220-2-rui.silva@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220331154536.1544220-1-rui.silva@linaro.org> References: <20220331154536.1544220-1-rui.silva@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the smsc lan91c9x and lan91c1xx controller device tree bindings documentation to json-schema. Signed-off-by: Rui Miguel Silva --- .../bindings/net/smsc,lan91c111.yaml | 61 +++++++++++++++++++ .../bindings/net/smsc-lan91c111.txt | 17 ------ 2 files changed, 61 insertions(+), 17 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/smsc,lan91c111.yaml delete mode 100644 Documentation/devicetree/bindings/net/smsc-lan91c111.txt diff --git a/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml new file mode 100644 index 000000000000..1730284430bc --- /dev/null +++ b/Documentation/devicetree/bindings/net/smsc,lan91c111.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller + +maintainers: + - Nicolas Pitre + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + const: smsc,lan91c111 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reg-shift: true + + reg-io-width: + enum: [ 1, 2, 4 ] + default: 4 + + reset-gpios: + description: GPIO connected to control RESET pin + maxItems: 1 + + power-gpios: + description: GPIO connect to control PWRDEWN pin + maxItems: 1 + + pxa-u16-align4: + description: put in place the workaround the force all u16 writes to be + 32 bits aligned + type: boolean + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + + ethernet@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = ; + reg-io-width = <2>; + }; diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt deleted file mode 100644 index 309e37eb7c7c..000000000000 --- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt +++ /dev/null @@ -1,17 +0,0 @@ -SMSC LAN91c111 Ethernet mac - -Required properties: -- compatible = "smsc,lan91c111"; -- reg : physical address and size of registers -- interrupts : interrupt connection - -Optional properties: -- phy-device : see ethernet.txt file in the same directory -- reg-io-width : Mask of sizes (in bytes) of the IO accesses that - are supported on the device. Valid value for SMSC LAN91c111 are - 1, 2 or 4. If it's omitted or invalid, the size would be 2 meaning - 16-bit access only. -- power-gpios: GPIO to control the PWRDWN pin -- reset-gpios: GPIO to control the RESET pin -- pxa-u16-align4 : Boolean, put in place the workaround the force all - u16 writes to be 32 bits aligned