From patchwork Fri Mar 25 22:08:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gwendal Grignou X-Patchwork-Id: 554475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 811DCC433F5 for ; Fri, 25 Mar 2022 22:08:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233782AbiCYWKP (ORCPT ); Fri, 25 Mar 2022 18:10:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233780AbiCYWKO (ORCPT ); Fri, 25 Mar 2022 18:10:14 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B59341667C6 for ; Fri, 25 Mar 2022 15:08:39 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id p8so7594053pfh.8 for ; Fri, 25 Mar 2022 15:08:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l98A4PNT9yRJjDO0lTIQbjMRwoPNVoAjqrcGwahNQ0U=; b=m0aqV6+DxvfENOsDf/vAN7uTs2V26xAaCIqes8qJ3+fyPF+/pw469P5ueBSSiBgX7n uXWkqXbSPZUDxSj83/F8nPRCMBNorjfRwN+2502PSgNj1WSz1IdnUusNiAgzCOq8QXGr L1zuwO8j8nY+a7OOpwPIup949JNFdvsxrDtCU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l98A4PNT9yRJjDO0lTIQbjMRwoPNVoAjqrcGwahNQ0U=; b=af+Uo02S8QJpMD8HXfa8Qx8rFv5ofguQIQO4p1c8PZJxh/839cd3vxxRrfu2Y2W9U1 fjvPQNJZ4ysqbq4M5kS1POCFrmcEkBbmu022LDxkSDVSQ1s4I1jYyR5nx7xlm/nFIBub /TLenME+sWcSRGtHBWkvlT74wD0j08xxRiEvgEPnolW8k+Xku2ZKjpXJrBw3VHcnlhm2 UPUHmThJ+G/pLoRsbQRYvjLJS0TIOkiWzZ5/Pb9vp97meTQWW8ZqV1BYoFt4YsrcLGRY 9e6GHev4QmrWCAOuJPHpuVnsEF/o9eSTS4+PTDqx6knY6e7niydvWFcsFZ8igqigDfs6 A0Ig== X-Gm-Message-State: AOAM5305Bfp+6vviqvsEctEDLFz+qBmmm5sLY8YW+AsWY7LuJweIn+hD yOcFxvmgwzmL5T2q/zDaFDuinoOBvjbtEw== X-Google-Smtp-Source: ABdhPJxKy1JgbsWnuseG13j2sQc5BR7i0UafZcVClms+W9xzwnhjmKakpMxa3fUFfmjPxguX6E/QTA== X-Received: by 2002:aa7:81c1:0:b0:4f7:6ba1:553b with SMTP id c1-20020aa781c1000000b004f76ba1553bmr12357364pfn.45.1648246119245; Fri, 25 Mar 2022 15:08:39 -0700 (PDT) Received: from localhost ([2620:15c:202:201:f21c:980b:7d64:94f9]) by smtp.gmail.com with UTF8SMTPSA id k17-20020a056a00135100b004fa9df39517sm8342482pfu.198.2022.03.25.15.08.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Mar 2022 15:08:38 -0700 (PDT) From: Gwendal Grignou To: jic23@kernel.org, robh+dt@kernel.org, swboyd@chromium.org Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, Gwendal Grignou Subject: [PATCH v3 6/8] iio: sx9324: Add Setting for internal compensation resistor Date: Fri, 25 Mar 2022 15:08:25 -0700 Message-Id: <20220325220827.3719273-7-gwendal@chromium.org> X-Mailer: git-send-email 2.35.1.1021.g381101b075-goog In-Reply-To: <20220325220827.3719273-1-gwendal@chromium.org> References: <20220325220827.3719273-1-gwendal@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Based on device tree setting, set the internal compensation resistor. Signed-off-by: Gwendal Grignou --- Changes since v2: - No changes. Changes since v1: - No changes. drivers/iio/proximity/sx9324.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/iio/proximity/sx9324.c b/drivers/iio/proximity/sx9324.c index 3f229dffd5380..38dfdc6dc86ad 100644 --- a/drivers/iio/proximity/sx9324.c +++ b/drivers/iio/proximity/sx9324.c @@ -52,6 +52,11 @@ #define SX9324_REG_CLK_SPRD 0x15 #define SX9324_REG_AFE_CTRL0 0x20 +#define SX9324_REG_AFE_CTRL0_RINT_MASK GENMASK(7, 6) +#define SX9324_REG_AFE_CTRL0_RINT_LOWEST 0x00 +#define SX9324_REG_AFE_CTRL0_RINT_LOW 0x40 +#define SX9324_REG_AFE_CTRL0_RINT_HIGH 0x80 +#define SX9324_REG_AFE_CTRL0_RINT_HIGHEST 0xc0 #define SX9324_REG_AFE_CTRL1 0x21 #define SX9324_REG_AFE_CTRL2 0x22 #define SX9324_REG_AFE_CTRL3 0x23 @@ -769,7 +774,7 @@ static const struct sx_common_reg_default sx9324_default_regs[] = { */ { SX9324_REG_GNRL_CTRL1, SX9324_REG_GNRL_CTRL1_PAUSECTRL }, - { SX9324_REG_AFE_CTRL0, 0x00 }, + { SX9324_REG_AFE_CTRL0, SX9324_REG_AFE_CTRL0_RINT_LOWEST }, { SX9324_REG_AFE_CTRL3, 0x00 }, { SX9324_REG_AFE_CTRL4, SX9324_REG_AFE_CTRL4_FREQ_83_33HZ | SX9324_REG_AFE_CTRL4_RES_100 }, @@ -855,6 +860,7 @@ sx9324_get_default_reg(struct device *dev, int idx, char prop[] = SX9324_PROXRAW_DEF; u32 start = 0, raw = 0, pos = 0; int ret, count, ph, pin; + const char *res; memcpy(reg_def, &sx9324_default_regs[idx], sizeof(*reg_def)); switch (reg_def->reg) { @@ -875,6 +881,22 @@ sx9324_get_default_reg(struct device *dev, int idx, SX9324_REG_AFE_PH0_PIN_MASK(pin); reg_def->def = raw; break; + case SX9324_REG_AFE_CTRL0: + ret = device_property_read_string(dev, + "semtech,int-comp-resistor", &res); + if (ret) + break; + reg_def->def &= ~SX9324_REG_AFE_CTRL0_RINT_MASK; + if (!strcmp(res, "lowest")) + reg_def->def |= SX9324_REG_AFE_CTRL0_RINT_LOWEST; + else if (!strcmp(res, "low")) + reg_def->def |= SX9324_REG_AFE_CTRL0_RINT_LOW; + else if (!strcmp(res, "high")) + reg_def->def |= SX9324_REG_AFE_CTRL0_RINT_HIGH; + else if (!strcmp(res, "highest")) + reg_def->def |= SX9324_REG_AFE_CTRL0_RINT_HIGHEST; + + break; case SX9324_REG_AFE_CTRL4: case SX9324_REG_AFE_CTRL7: if (reg_def->reg == SX9324_REG_AFE_CTRL4)