From patchwork Thu Mar 17 16:23:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 552748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B21BDC433EF for ; Thu, 17 Mar 2022 16:24:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236504AbiCQQZe (ORCPT ); Thu, 17 Mar 2022 12:25:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236506AbiCQQZd (ORCPT ); Thu, 17 Mar 2022 12:25:33 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3F814BD2CA for ; Thu, 17 Mar 2022 09:24:17 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0C8E015A1; Thu, 17 Mar 2022 09:24:17 -0700 (PDT) Received: from donnerap.arm.com (donnerap.cambridge.arm.com [10.1.196.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4B16B3F7B4; Thu, 17 Mar 2022 09:24:15 -0700 (PDT) From: Andre Przywara To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Rob Herring , Mesih Kilinc , Icenowy Zheng , Jesse Taube , Giulio Benetti , George Hilliard , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev Subject: [PATCH v2 06/12] ARM: dts: suniv: F1C100: fix CPU node Date: Thu, 17 Mar 2022 16:23:43 +0000 Message-Id: <20220317162349.739636-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220317162349.739636-1-andre.przywara@arm.com> References: <20220317162349.739636-1-andre.przywara@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The /cpu node in the f1c100s.dtsi is not spec compliant, it's missing the reg property, and the corresponding address and size cells properties. Add them to make the bindings check pass. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 922efd5e9457..0a7fa37bbd24 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -29,9 +29,13 @@ osc32k: clk-32k { }; cpus { - cpu { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { compatible = "arm,arm926ej-s"; device_type = "cpu"; + reg = <0x0>; }; };