From patchwork Thu Mar 17 09:31:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas tanure X-Patchwork-Id: 552779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E52FBC433EF for ; Thu, 17 Mar 2022 09:32:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231920AbiCQJdO (ORCPT ); Thu, 17 Mar 2022 05:33:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231883AbiCQJdI (ORCPT ); Thu, 17 Mar 2022 05:33:08 -0400 Received: from mx0b-001ae601.pphosted.com (mx0b-001ae601.pphosted.com [67.231.152.168]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D3B01D4C21; Thu, 17 Mar 2022 02:31:52 -0700 (PDT) Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22H7ecZn022935; Thu, 17 Mar 2022 04:31:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=ZutywnvGieAXBdRDLuKwEdovEb7EswsUO9vvyJbYT3U=; b=rEZUjnOeyG7oBUj6BNAbDOEhyL3IUNBPUts+YJ260XbUwiDRwM2TkR8qhzORaVygBf4Q UgcnHMW1CRWf+JCGdIA+uES9ChwRGi0B56oDXcp0b14POnE62tO0pig6DYngC5571CPh VIodlfT9ztCEoX5015pKKGkm8oi7SwPdmrcLwvRrMoZCH26WGmrl8A26wfUOAlUQz0Z2 9/LAYuBQiWGO2JIV9V7oz2cHvYLfySkPLjahci3EZGIUg7UuwJQppuu1jtAK6Ay3nLXl 4nzeit4X9Ke+UxBevZmH4C/8UmN/aUp4mpkMfZRzA0LTkFcxHL+sli/SWFOa4Dl7HNRj lw== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0b-001ae601.pphosted.com (PPS) with ESMTPS id 3et5yp475f-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 17 Mar 2022 04:31:32 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 17 Mar 2022 09:31:30 +0000 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.18 via Frontend Transport; Thu, 17 Mar 2022 09:31:30 +0000 Received: from aryzen.ad.cirrus.com (unknown [198.61.64.95]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 9A5B8B1A; Thu, 17 Mar 2022 09:31:30 +0000 (UTC) From: Lucas Tanure To: Liam Girdwood , Mark Brown , Rob Herring , Jaroslav Kysela , Takashi Iwai CC: , , , , Lucas Tanure , Charles Keepax Subject: [PATCH v4 03/16] sound: cs35l41: Move cs35l41_gpio_config to shared lib Date: Thu, 17 Mar 2022 09:31:07 +0000 Message-ID: <20220317093120.168534-4-tanureal@opensource.cirrus.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220317093120.168534-1-tanureal@opensource.cirrus.com> References: <20220317093120.168534-1-tanureal@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: tfLNoz1vuMv3JKNXedM-0ldhWi_CufX6 X-Proofpoint-GUID: tfLNoz1vuMv3JKNXedM-0ldhWi_CufX6 X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ASoC and HDA can use a single function to configure the chip gpios. Signed-off-by: Lucas Tanure Acked-by: Charles Keepax --- include/sound/cs35l41.h | 1 + sound/pci/hda/cs35l41_hda.c | 11 ++++----- sound/soc/codecs/cs35l41-lib.c | 41 +++++++++++++++++++++++++++++++ sound/soc/codecs/cs35l41.c | 44 +--------------------------------- 4 files changed, 48 insertions(+), 49 deletions(-) diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h index 4200379e0c26..e312eb1f6e48 100644 --- a/include/sound/cs35l41.h +++ b/include/sound/cs35l41.h @@ -798,5 +798,6 @@ int cs35l41_set_channels(struct device *dev, struct regmap *reg, unsigned int rx_num, unsigned int *rx_slot); int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, int boost_cap, int boost_ipk); +int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg); #endif /* __CS35L41_H */ diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index a14ad3b0d516..e00ceaca79c0 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -235,12 +235,11 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) case CS35L41_NOT_USED: break; case CS35l41_VSPK_SWITCH: - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO1_CTRL_MASK, 1 << CS35L41_GPIO1_CTRL_SHIFT); + hw_cfg->gpio1.func = CS35L41_GPIO1_GPIO; + hw_cfg->gpio1.out_en = true; break; case CS35l41_SYNC: - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO1_CTRL_MASK, 2 << CS35L41_GPIO1_CTRL_SHIFT); + hw_cfg->gpio1.func = CS35L41_GPIO1_MDSYNC; break; default: dev_err(cs35l41->dev, "Invalid function %d for GPIO1\n", @@ -254,8 +253,6 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) case CS35L41_NOT_USED: break; case CS35L41_INTERRUPT: - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO2_CTRL_MASK, 2 << CS35L41_GPIO2_CTRL_SHIFT); break; default: dev_err(cs35l41->dev, "Invalid GPIO2 function %d\n", hw_cfg->gpio2.func); @@ -263,6 +260,8 @@ static int cs35l41_hda_apply_properties(struct cs35l41_hda *cs35l41) } } + cs35l41_gpio_config(cs35l41->regmap, hw_cfg); + if (internal_boost) { cs35l41->reg_seq = &cs35l41_hda_reg_seq_int_bst; ret = cs35l41_boost_config(cs35l41->dev, cs35l41->regmap, diff --git a/sound/soc/codecs/cs35l41-lib.c b/sound/soc/codecs/cs35l41-lib.c index 905c648a8f49..eeeaeaa0db82 100644 --- a/sound/soc/codecs/cs35l41-lib.c +++ b/sound/soc/codecs/cs35l41-lib.c @@ -1040,6 +1040,47 @@ int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_in } EXPORT_SYMBOL_GPL(cs35l41_boost_config); +int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg) +{ + struct cs35l41_gpio_cfg *gpio1 = &hw_cfg->gpio1; + struct cs35l41_gpio_cfg *gpio2 = &hw_cfg->gpio2; + int irq_pol = IRQF_TRIGGER_NONE; + + regmap_update_bits(regmap, CS35L41_GPIO1_CTRL1, + CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, + gpio1->pol_inv << CS35L41_GPIO_POL_SHIFT | + !gpio1->out_en << CS35L41_GPIO_DIR_SHIFT); + + regmap_update_bits(regmap, CS35L41_GPIO2_CTRL1, + CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, + gpio2->pol_inv << CS35L41_GPIO_POL_SHIFT | + !gpio2->out_en << CS35L41_GPIO_DIR_SHIFT); + + if (gpio1->valid) + regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO1_CTRL_MASK, + gpio1->func << CS35L41_GPIO1_CTRL_SHIFT); + + if (gpio2->valid) { + regmap_update_bits(regmap, CS35L41_GPIO_PAD_CONTROL, CS35L41_GPIO2_CTRL_MASK, + gpio2->func << CS35L41_GPIO2_CTRL_SHIFT); + + switch (gpio2->func) { + case CS35L41_GPIO2_INT_PUSH_PULL_LOW: + case CS35L41_GPIO2_INT_OPEN_DRAIN: + irq_pol = IRQF_TRIGGER_LOW; + break; + case CS35L41_GPIO2_INT_PUSH_PULL_HIGH: + irq_pol = IRQF_TRIGGER_HIGH; + break; + default: + break; + } + } + + return irq_pol; +} +EXPORT_SYMBOL_GPL(cs35l41_gpio_config); + MODULE_DESCRIPTION("CS35L41 library"); MODULE_AUTHOR("David Rhodes, Cirrus Logic Inc, "); MODULE_AUTHOR("Lucas Tanure, Cirrus Logic Inc, "); diff --git a/sound/soc/codecs/cs35l41.c b/sound/soc/codecs/cs35l41.c index 90dec80707ea..d25689fe0c60 100644 --- a/sound/soc/codecs/cs35l41.c +++ b/sound/soc/codecs/cs35l41.c @@ -1017,48 +1017,6 @@ static int cs35l41_set_pdata(struct cs35l41_private *cs35l41) return 0; } -static int cs35l41_gpio_config(struct cs35l41_private *cs35l41) -{ - struct cs35l41_gpio_cfg *gpio1 = &cs35l41->hw_cfg.gpio1; - struct cs35l41_gpio_cfg *gpio2 = &cs35l41->hw_cfg.gpio2; - int irq_pol = IRQF_TRIGGER_NONE; - - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO1_CTRL1, - CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, - gpio1->pol_inv << CS35L41_GPIO_POL_SHIFT | - !gpio1->out_en << CS35L41_GPIO_DIR_SHIFT); - - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO2_CTRL1, - CS35L41_GPIO_POL_MASK | CS35L41_GPIO_DIR_MASK, - gpio2->pol_inv << CS35L41_GPIO_POL_SHIFT | - !gpio2->out_en << CS35L41_GPIO_DIR_SHIFT); - - if (gpio1->valid) - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO1_CTRL_MASK, - gpio1->func << CS35L41_GPIO1_CTRL_SHIFT); - - if (gpio2->valid) { - regmap_update_bits(cs35l41->regmap, CS35L41_GPIO_PAD_CONTROL, - CS35L41_GPIO2_CTRL_MASK, - gpio2->func << CS35L41_GPIO2_CTRL_SHIFT); - - switch (gpio2->func) { - case CS35L41_GPIO2_INT_PUSH_PULL_LOW: - case CS35L41_GPIO2_INT_OPEN_DRAIN: - irq_pol = IRQF_TRIGGER_LOW; - break; - case CS35L41_GPIO2_INT_PUSH_PULL_HIGH: - irq_pol = IRQF_TRIGGER_HIGH; - break; - default: - break; - } - } - - return irq_pol; -} - static int cs35l41_component_probe(struct snd_soc_component *component) { struct cs35l41_private *cs35l41 = snd_soc_component_get_drvdata(component); @@ -1366,7 +1324,7 @@ int cs35l41_probe(struct cs35l41_private *cs35l41, const struct cs35l41_hw_cfg * cs35l41_test_key_lock(cs35l41->dev, cs35l41->regmap); - irq_pol = cs35l41_gpio_config(cs35l41); + irq_pol = cs35l41_gpio_config(cs35l41->regmap, &cs35l41->hw_cfg); /* Set interrupt masks for critical errors */ regmap_write(cs35l41->regmap, CS35L41_IRQ1_MASK1,